EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 95

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–60. DSP Block Interface to Interconnect
Altera Corporation
October 2007
C4 Interconnect
LAB
18
f
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
36
16
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed and unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface. The LAB row source for control
signals, data inputs, and outputs is shown in
Refer to the
Stratix II GX Device Handbook for more information on DSP blocks.
Row Interface
36
12
Block
DSP Blocks in Stratix II GX Devices
36 Inputs per Row
R4 Interconnect
16
Control
A[17..0]
B[17..0]
DSP Block
Row Structure
Stratix II GX Device Handbook, Volume 1
OA[17..0]
OB[17..0]
36 Outputs per Row
Direct Link Outputs
to Adjacent LABs
36
Table
36
chapter in volume 2 of the
Stratix II GX Architecture
2–23.
Direct Link Interconnect
from Adjacent LAB
LAB
2–87