EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 124

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

I/O Structure
Figure 2–80. Control Signal Selection per IOE
Note to
(1)
2–116
Stratix II GX Device Handbook, Volume 1
Dedicated I/O
Clock [7..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their
control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive
the I/O local interconnect, which then drives the control selection multiplexers.
Figure
2–80:
io_oe
io_sclr
io_aclr
io_ce_out
io_ce_in
io_clk
In normal bidirectional operation, you can use the input register for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. You can use the OE register for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects.
shows the IOE in bidirectional configuration.
clk_in
Note (1)
clk_out
ce_in
ce_out
aclr/apreset
Altera Corporation
sclr/spreset
October 2007
Figure 2–81
oe