EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 40

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Transceivers
Figure 2–25. Stratix II GX Block in Parallel Loopback Mode
2–32
Stratix II GX Device Handbook, Volume 1
FPGA
Logic
Array
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
RX Phase
Compen-
Verify
BIST
BIST
sation
FIFO
Compensation
TX Phase
FIFO
Ordering
Serializer
Byte
Byte
Figure 2–25
Reverse Serial Loopback
The reverse serial loopback mode uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, passes through the CRU
unit, and the retimed serial data is looped back and transmitted though
the high-speed differential transmitter output buffer.
20
serializer
Byte
De-
Encoder
8B/10B
shows the data path in parallel loopback mode.
BIST PRBS
Generator
Decoder
8B/10B
Match
Rate
FIFO
Deskew
FIFO
PRBS
BIST
Verify
Loopback
Parallel
Aligner
Word
Analog Receiver and
Transmitter Logic
Serializer
serializer
De-
Altera Corporation
Recovery
October 2007
Clock
Unit