EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 253

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

(1)
Input delay
from pin to
internal
cells
Input delay
from pin to
input
register
Delay from
output
register to
output pin
Output
enable pin
delay
Table 4–81. Stratix II GX IOE Programmable Delay on Row Pins
Parameter
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest
version of the Quartus II software.
Pad to I/O
dataout to
logic array
Pad to I/O
input
register
I/O output
register to
pad
t
XZ
Affected
Paths
, t
ZX
Available
Settings
64
8
2
2
Default Capacitive Loading of Different I/O Standards
See
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
Table 4–82. Default Loading of Different I/O Standards for Stratix II GX
Devices (Part 1 of 2)
Table 4–82
Offset
Min
Minimum
0
0
0
0
Timing
Offset
1782
2054
Max
332
320
I/O Standard
for default capacitive loading of different I/O standards.
Offset
Min
-3 Speed
0
0
0
0
Grade
Offset
2876
3270
Max
500
483
Offset
Min
0
0
0
0
-3 Speed
Grade
Note (1)
Offset
3020
3434
Max
525
507
Capacitive Load
Offset
Min
-4 Speed
0
0
0
0
10
10
0
0
0
0
0
0
0
Grade
Offset
3212
3652
Max
559
539
Offset
Min
-5 Speed
0
0
0
0
Grade
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Offset
3853
4381
Max
670
647
Unit
ps
ps
ps
ps