EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 99

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–62. Regional Clocks
Altera Corporation
October 2007
CLK[3..0]
7
1
2
8
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant), which allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure
RCLK
RCLK
[3..0]
[7..4]
2–63. Corner PLLs cannot drive dual-regional clocks.
[31..28]
[11..8]
RCLK
RCLK
CLK[15..12]
CLK[7..4]
11 5
12 6
[27..24]
[15..12]
RCLK
RCLK
Stratix II GX Device Handbook, Volume 1
[23..20]
[19..16]
RCLK
RCLK
Stratix II GX
Stratix II GX
Transceiver
Transceiver
Block
Block
Stratix II GX Architecture
2–91