EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 98

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

PLLs and Clock Networks
Figure 2–61. Global Clocking
2–90
Stratix II GX Device Handbook, Volume 1
CLK[3..0]
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout.
pins driving global clock networks.
Regional Clock Network
There are eight regional clock networks (RCLK[7..0]) in each quadrant
of the Stratix II GX device that are driven by the dedicated
CLK[15..12]and CLK[7..0] input pins, by PLL outputs, or by internal
logic. The regional clock networks provide the lowest clock delay and
skew for logic contained in a single quadrant. The CLK pins
symmetrically drive the RCLK networks in a particular quadrant, as
shown in
Figure
Global Clock [15..0]
2–62.
CLK[7..4]
CLK[15..12]
Figure 2–61
Global Clock [15..0]
shows the 12 dedicated CLK
Altera Corporation
October 2007