CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 10

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Dark Level
A SPI controlled DAC provides the programmable gain
amplifiers with a dark level. This analog voltage corresponds with
the all zero output of the ADC. This dark level is tuned to
optimally use the ADC range.
The dark level coming from the pixels follow a Gaussian
distribution. This distribution is visible in a dark image as the
FPN. The spread on the distribution is influenced by the dark
current and temperature. Typically the spread is 100 mV peak to
peak.
The average dark level of this distribution depends on several
parameters:
■
■
■
The combination of these parameters adds an offset to the dark
level. The offset is in the order of magnitude of 200 mV.
To allow off-chip FPN calibration, the full spread on the dark level
is mapped inside the range of the ADC. To optimally use the input
range of the ADC, the spread on the dark level is mapped as
close as possible to the high level of the ADC’s input range.
The default startup value of the dark level coming from the DAC
is 1.5 V. This ensures that the spread on the dark level is
completely mapped in the range of the ADC. The startup DAC
dark level is not optimal. By taking a dark image after startup, the
offset on the dark image histogram is measured. The offset from
the optimal case is subtracted from the dark level coming from
the DAC. This places the dark level distribution optimally inside
the range of the ADC. This procedure is followed after every
change in operation condition such as temperature, FOT timing,
and ROT.
Analog to Digital Converters
LUPA 3000 includes 64 pipelined 9-bit analog to digital
converters (ADCs) operating at approximately 25.75 mega
samples per second (MSPS). Two ADCs are combined to
provide digitized data to one of the 32 LVDS serialization
channels. One of the ADC pair converts data from an “odd
kernel” of the LUPA 3000 pixel array, the other from an ‘even
kernel”. LUPA 3000 only processes the eight MSBs of the
converter to realize an improved noise performance 8-bit
converter.
The ADCs are designed using fully differential circuits to improve
performance and noise immunity. In addition, an RSD
(redundant signed digit) 1.5 bit per stage architecture with digital
error correction is used to improve DNL and ensure that no
codes are missing. Interstage ADC gain errors are addressed
using
Auto-zeroing and other calibration methods are implemented to
remove offsets.
The ADCs digitize up to a maximum of one volt signals from the
pixel array core. This provides a maximum internal dynamic
range to the ADC of two Vp-p (bipolar differential). The dynamic
range is set by the difference of the Vrefp-Vrefm reference levels.
The reference levels are available at LUPA 3000 package pins
for external decoupling.
Document Number: 001-44335 Rev. *C
The processing corner
Tolerances on the pixel power supplies (Vpix, Vreset, Vmem_l,
and Vmem_h)
Pixel timing
commutation
techniques
for
capacitor
PRELIMINARY
matching.
References and Programmable Trimming
Bits 6:4 of SPI register 64 (decimal) allow adjustment of the
Vrefp-Vrefm differential ADC reference level. Eight settings are
provided to enable trimming of the dynamic range. Reduced
dynamic range is used to optimize signals in low light intensity,
where reduced pixel levels require further gain.
the permitted trim settings.
Table 9. Programmable ADC Reference Level
The black voltage level from the pixel array is more positive than
the user set Vdark or “black” reference level. This results in a
nonzero differential voltage in the PGAs and other AFE stages.
This condition prevents obtaining a desired 0 code out of the
ADCs. The 0.95x and 0.91x trim settings are specifically supplied
to allow minor adjustment to the ADC differential reference
(Vrefp-Vrefm) to ensure a 0 level code in these conditions.
The additional trim settings are provided as dynamic range
adjustments in low light intensities to act as effective global gain
settings. The absolute level of gain (from the typical values) are
not guaranteed. However, the gain increases are monotonic.
Approximately 2x (+6.0 dB) is the maximum gain obtainable
using this method. As a result, the combined gain of both PGAs
and the ADC reference trimming available is 8x maximum.
Some reference voltages are overdriven after the on-chip control
logic is powered down (refer section
Reference and Current Biasing
feature intended for testing and debugging, is not recommended
for normal operation. The reference voltages that are overdriven
are:
■
■
■
■
Table 10
parameters.
Register Address 64
Vrefp - Vrefm (can be overdriven as a pair)
Vcm
Vdark
Internal bandgap voltage
Bit 6
0
0
0
0
1
1
1
1
(dec)
summarizes the ADC and AFE (signal processing)
Bit 5 Bit 4
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Gain Level (typ)
Vrefp-Vrefm
0.67x
0.71x
0.77x
0.83x
0.91x
0.95x
1.0 x
0.5x
on page 16). Overdriving, a
CYIL1SN3000AA
+6.0 dB (2x)
Available setting to
ensure 0 code
Available setting to
ensure 0 code
POR (startup) default
level
Maximum effective gain
On-Chip BandGap
Comments
Table 9
Page 10 of 61
provides
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