CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 33

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI )
The SPI registers have an address space of 7 bits, a<6>–a<0>,
and 8 data bits, d<7>–d<0>. A single instruction bit chooses
between a read or write instruction.
The SPI is used only after the clock has started and the chip is
not in reset. Otherwise the SPI register is kept in reset. SPI
registers are reset to their default value by bringing RESET_N
low. The SPI bit RESET_N_SEQ has no effect on the SPI bits.
Setup and hold requirements of interface signals relative to
SPI_CLK are for both requirements 2.5 ns. Output delay is 1.5 ns
after falling edge of SPI_CLK. Rise time (10%–90%) is 9 ns
assuming a 18 pF load. To upload SPI, follow this sequence:
Disable Sequencer → Upload through SPI → ENable Sequencer
Write Sequence, C=1
The image sensor is selected by pulling CS low. The WRITE instruction is issued, followed by the 7-bit address, and then the 8-bit
data. All data is clocked in on the rising edge of the clock.
To write the data to the array, the CS is brought high after the least significant bit (D0) of the data byte is clocked in. If CS is brought
high at any other time, the write operation is not completed. Maximum operating frequency is 10 MHz.
Document Number: 001-44335 Rev. *C
PRELIMINARY
Figure 14. SPI Read Timing
Figure 15. SPI Write Timing
Read Sequence, C=0
The part is selected by pulling CS low. The 1-bit instruction
(READ) is transmitted to the image sensor, followed by the 7-bit
address (A6 through A0). The instruction and address bits are
clocked in on the rising edge of the clock. After the correct READ
instruction and address are sent, the data stored in the memory
at the selected address is shifted out on the MISO pin. The data
bits are shifted out on the first falling edge after the last address
bit is clocked. The read operation is terminated by raising the CS
pin. The maximum operating frequency is 10 MHz.
Note SPI settings cannot be uploaded during readout.
CYIL1SN3000AA
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