CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 9

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6T Pixel Architecture
The pixel architecture shown in
shutter combined with a high sensitivity and good Parasitic Light
Sensitivity (PLS). This pixel architecture is designed in an 8 µm
x 8 µm pixel pitch and designed with a large fill factor to meet the
electro-optical specifications as shown in
Figure 7. Pixel Schematic
Table 8. Programmable Amplifiers Gain Settings
The gain is set through bits 2:0 in register 73 (decimal).
The gain register controls the gain setting globally for all 64 PGA
and ADC channels.
Document Number: 001-44335 Rev. *C
reset
Bit 2
0
0
0
0
1
1
1
Vin
Vin
from Column
from Column
Amps
Amps
1.4V to 0.4V
1.4V to 0.4V
1 volt peak
1 volt peak
max.
max.
~ 1.4 -1.5V
~ 1.4 -1.5V
Vref_Blk
Vref_Blk
Register Address d73
precharge
sample
Overview: HDI1 Analog Front-end (Signal Conditioning + Gain) and ADC Concept
Overview: HDI1 Analog Front-end (Signal Conditioning + Gain) and ADC Concept
Bit 1
0
0
1
1
0
0
1
Single to
Single to
Single to
Single to
Unipolar
Unipolar
Unipolar
Unipolar
Diff
Diff
Diff
Diff
Gain Decoder : 6 settings
Gain Decoder : 6 settings
1x, 1.5x, 2x, 2.25x, 3x, 4x
1x, 1.5x, 2x, 2.25x, 3x, 4x
1x, 1.5x, or 2x
1x, 1.5x, or 2x
Figure 7
+
+
+
+
-
-
-
-
2.5 - 3.3V
Vmem
Vcm
Vcm
Unipolar Diff
Unipolar Diff
1 Vpp max
1 Vpp max
Figure 8. TAnalog Frontend and ADC Concept
Table 2
3 bits from SPI
3 bits from SPI
features the global
PRELIMINARY
Row sel.
Bit 0
on page 3.
Unipolar
Unipolar
Unipolar
Unipolar
Diff
Diff
Diff
Diff
0
1
0
1
0
1
x
1x, 1.5x, or 2x
1x, 1.5x, or 2x
+
+
+
+
-
-
-
-
Vcm
Vcm
Ibias (from master Ibias gen)
Ibias (from master Ibias gen)
ADC/OTA Bias Voltage Gen
ADC/OTA Bias Voltage Gen
Unipolar Diff
Unipolar Diff
1 Vpp max
1 Vpp max
2.25x
Analog Front End
Programmable Gain Amplifiers
LUPA 3000 includes analog programmable gain amplifiers
(before each of the 64 ADCs) to maximize sensor array signal
levels to the ADC dynamic range. Six gain settings are available
through the SPI register interface to allow 1x, 1.5x, 2x, 2.25x, 3x,
or 4x gain.
The entire “analog front end” signal processing and ADC concept
for the LUPA 3000 chip are shown in
The analog signal processing “frontend” circuits provide
programmable gain level. They also convert the single ended
pixel voltage from each column (as referenced to the user
programmable Black or Dark reference level) to a “unipolar”
differential signal for the PGA (programmable gain amplifier)
stages. This is followed by a conversion to a “bipolar” differential
signal to maximize the ADC dynamic range and noise immunity.
1.5x
2.0x
3.0x
4.0x
3.0x
A latency (delay) is incurred for the analog signal processing,
PGA, and ADC stages. The total latency is 44 high speed input
clock delays. The output synchronization signals from the LVDS
“sync” channel factor in this latency.
1x
4
4
Gain Level
2x (full diff)
2x (full diff)
Uni
Uni
Uni
Uni
To Bipolar
To Bipolar
To Bipolar
To Bipolar
Diff
Diff
Diff
Diff
+
+
+
+
-
-
-
-
Bipolar Diff
Bipolar Diff
2 Vpp max
2 Vpp max
Vcm
Vcm
SC Clock Gen (non-overlapping)
SC Clock Gen (non-overlapping)
Vrefm
Vrefm
Vrefm
Vrefm
Vrefp
Vrefp
Vrefp
Vrefp
POR default value
Do not use (Redundant gain codes)
9 bit @ 27 MSPS
9 bit @ 27 MSPS
9 bit @ 27 MSPS
9 bit @ 27 MSPS
Pipelined ADC
Pipelined ADC
Pipelined ADC
Pipelined ADC
RDS (1.5 bits/stage)
RDS (1.5 bits/stage)
RDS (1.5 bits/stage)
RDS (1.5 bits/stage)
ADC Clock (i.e. 27 MHz)
ADC Clock (i.e. 27 MHz)
6
6
CYIL1SN3000AA
Comments
Figure
D8:D0 (9 bits)
D8:D0 (9 bits)
D8:D0 (9 bits)
D8:D0 (9 bits)
8.
Page 9 of 61
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