CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 42

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reduced ROT Readout Mode
After selecting a pixel row, the pixels need to charge a large
capacitive load. This load is caused by the long metal line
connecting all the pixels of a column and by the number of pixels
that are connected to this line. As a result, it takes a long time to
charge this line. The column load transistors act as a current
source that is a load to the source follower inside the pixel. If the
current source draws more current, the settle time on the
columns is faster. However, the drawback is a higher power
dissipation of the 1696 column in parallel.
In reduced ROT mode, the settle time on the columns are limited
by using the large capacitive load of the column itself as a
sampling capacitor. The column load current is not needed any
more and the rise time on the columns is shorter. By going to a
very short ROT (100-120 ns), the dynamic range becomes less.
By going to a normal ROT, the dynamic range becomes equal or
larger than in non reduced ROT mode, and the power
consumption is less.
The sensor operates in reduced ROT by default, with a ROT of
nine sensor clock periods (175 ns).
Asynchronous Reset
The sensor has a reset pin, RESET_N, and a reset SPI register,
RESET_N_SEQ. Both are active low.
RESET_N is the chip reset. All components on the chip are reset
when this pin is low. This includes the sequencer, the SPI
register, and X and Y shift registers. The reset is asynchronous.
RESET_N_SEQ is the sequencer reset. Bringing this bit low only
resets the sequencer. This is used to restart the sequencer with
the current SPI settings.
Document Number: 001-44335 Rev. *C
SEN_CLK
ROT pin
SEN_CLK
sync_x
FOT pin
clk_y
vmem
clk_y
PRELIMINARY
actual FOT (FOT_TIMER * 4 SEN_CLK)
actual ROT (ROT_TIMER + 2 SEN_CLK)
Figure 30. ROT Pin Timing
Figure 29. FOT Pin Timing
FOT and ROT Pin Timing
The chip has two pins (FOT and ROT) that indicate internal FOT
and ROT periods.
FOT Pin
The actual FOT goes from the falling edge of the internal VMEM
signal to the rising edge of the first internal CLK_Y. After this
rising edge of CLK_Y, the first ROT starts. The FOT pin goes high
at the same moment VMEM goes low and remains high until one
sensor clock period (CLKIN/4) before the end of the actual FOT.
This is shown in
ROT Pin
The actual ROT goes from the rising edge of the internal CLK_Y
signal to the falling edge of the internal SYNC_X signal. The ROT
pin goes high at the rising edge of CLK_Y and remains high until
one sensor clock (CLKIN/4) before the end of the actual ROT.
Table 49. FOT and ROT Pin Timing
Reset on Startup
When the sensor starts up, RESET_N is kept low until all supply
voltages are stable. After the rising edge of RESET_N,
RESET_N_SEQ is kept low for an additional 0.5 µs.
During the chip reset the data on the LVDS outputs (data
channels and sync channel) is invalid. When the chip comes out
of reset, but the sequencer is kept in reset, the LVDS outputs
toggle between the idle words.
ROT
FOT
Pin
Delay vs. Sensor Clock
Figure
2.5 ns
2.5 ns
29.
1 SEN_CLK
1 SEN_CLK
CYIL1SN3000AA
Rise and Fall Times
(20 pF Load)
6 ns
6 ns
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