CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 19

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14. Detailed Description of SPI Registers (continued)
Detailed Description of Internal Registers
All registers are reset to their default value when RESET_N is
low. When the chip is not in reset, all registers are written and
read through the SPI interface. The registers are written when
the on-chip sequencer is in reset (RESET_N_SEQ bit is low).
Resetting the sequencer has no influence on the SPI registers.
Registers are written during normal operation. However, this
influences image characteristics such as black level or interrupts
readout. To avoid this, change registers at the appropriate
moment during operation.
Registers that control the readout and reference voltages are
changed during the FOT (when FOT pin is high). Registers that
are used for pixel timing are changed outside the FOT (when
FOT pin is low). Change SPI registers when the RESET_N_SEQ
bit is low.
Document Number: 001-44335 Rev. *C
Address
102
103
104
105
106
107
108
109
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
111
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
Bits
Testpattern 6
Testpattern 7
Testpattern 8
Testpattern 9
Testpattern 10
Testpattern 11
Testpattern 12
Testpattern 13
Testpattern 14
Testpattern 15
Testpattern 16
Testpattern 17
Testpattern 18
Testpattern 19
Testpattern 20
Testpattern 21
Testpattern 22
Testpattern 23
Testpattern 24
Testpattern 25
Testpattern 26
Testpattern 27
Testpattern 28
Testpattern 29
Testpattern 30
Testpattern 31
PRELIMINARY
Name
SPI Registers
Sequencer Register (b0000000 / d0)
The sequencer register controls the power down of the analog
core and the different modes of the sequencer. Bits <7:6> are
ignored. The sequencer register contains several sub registers.
■
■
■
Powerdown, bit <0>. Setting this bit high brings the image
core in power down mode. It shuts down all analog amplifiers.
Reset_n_seq, bit<1>. Bringing this bit low resets the on-chip
sequencer. This allows interruption of light integration and
readout. Bringing the bit high triggers a new readout and
integration cycle in the sequencer.
Red_ROT, bit<2>. Setting this bit activates the reduced ROT
mode. This mode allows increasing the frame rate at a possibly
reduced dynamic range. The reduction in dynamic range
depends on the length of the ROT .
/ d1)”
so there is no reduction in dynamic range.
Test pattern for channel 6
Test pattern for channel 7
Test pattern for channel 8
Test pattern for channel 9
Test pattern for channel 10
Test pattern for channel 11
Test pattern for channel 12
Test pattern for channel 13
Test pattern for channel 14
Test pattern for channel 15
Test pattern for channel 16
Test pattern for channel 17
Test pattern for channel 18
Test pattern for channel 19
Test pattern for channel 20
Test pattern for channel 21
Test pattern for channel 22
Test pattern for channel 23
Test pattern for channel 24
Test pattern for channel 25
Test pattern for channel 26
Test pattern for channel 27
Test pattern for channel 28
Test pattern for channel 29
Test pattern for channel 30
Test pattern for channel 31
on page 20. The default timing is in reduced ROT mode,
Description
CYIL1SN3000AA
See “ROT_timer (b0000001
Page 19 of 61
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