CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 12

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Block
The data block is positioned in between the analog front end
(output stage+ADCs) and the LVDS interface. It muxes the
outputs of two ADCs to one LVDS block and performs some
minor data handling:
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■
LVDS
LUPA 3000 uses LVDS (low voltage differential signaling) I/O.
LVDS offers low power and low noise coupling. It also offers low
EMI emissions that are essential for the high data readout rates
that are required by the LUPA 3000 image sensor. LVDS voltage
swings range from 250 mV to 450 mV with a typical of 350 mV.
Because of the low voltage swings, rise and fall times are
reduced, enabling higher operating speeds than CMOS, TTL, or
other drivers operating at the same slew rate. It uses a common
mode voltage ~1.2 V to 1.25 V above ground, and as a result is
more independent of the power supply level and less susceptible
to noise. Differential transmission also reduces EMI levels. The
2-pin differential output drives a cable with approximately 100 Ω
characteristic impedance, which is “far-end” terminated with
100 Ω.
LVDS Data Channels
LUPA 3000 has 32 LVDS data output channels operating at a
DDR (Double Date Rate) of 412 Mb per second (typical) using a
206 MHz input clock. The LVDS data channels have a high
speed parallel to the serial converter logic function (serializer)
that serializes the 52 MS per second 8-bit parallel data from a
Document Number: 001-44335 Rev. *C
CRC calculation and insertion
Training and test pattern generation
PRELIMINARY
Figure 10. Data Block
It also contains a huge part of the functionality for black level
calibration.
A number of data blocks are placed in parallel to serve all data
output channels. One additional channel generates the synchro-
nization protocol. A high level overview is illustrated in the
following figure.
time multiplexed odd and even kernel ADC pair. The high speed
serial bit stream drives a LVDS output driver.
The LVDS driver must deliver positive or negative current
through a 2-pin differential output to represent a logical 1 and
logical 0 state respectively. The driver is designed in compliance
with the ANSI/TIA/EIA-644-A-2001 standard. The circuit consists
of a programmable current sink that defines the drive current, a
dynamically controlled current source, a 4-transistor bridge that
steers these currents to the differential outputs, and a common
mode feedback circuit to balance the sink and source currents.
The LVDS standard defines the drive current between 2.5 to
4.5 mA. The termination resistance is specified from 90 Ω to
132 Ω. To allow flexibility in power consumption, the output drive
current is programmed through the SPI register interface.
Settings are available for operation outside the specified ANSI
standard to allow custom settings for power and speed
enhancements. These settings may require the use of
nonstandard termination resistance. Current drive programming
is accomplished using bits 3:0 of SPI register 72 (decimal – LVDS
trim).
output current settings.
Figure 11
on page 13 defines the programmable LVDS
CYIL1SN3000AA
Page 12 of 61
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