DS3104GN Maxim Integrated Products, DS3104GN Datasheet
DS3104GN
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DS3104GN Summary of contents
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... Ordering Information PART TEMP RANGE DS3104GN -40C to +85C DS3104GN+ -40C to +85C +Denotes a lead(Pb)-free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’ ...
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DS3104-SE 1. STANDARDS COMPLIANCE ..........................................................................................................6 2. APPLICATION EXAMPLE ...............................................................................................................7 3. BLOCK DIAGRAM ...........................................................................................................................8 4. DETAILED DESCRIPTION ..............................................................................................................9 5. DETAILED FEATURES .................................................................................................................11 5 NPUT LOCK EATURES 5 IMING ARD TO INE ARD 5.3 ...
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DS3104-SE 7.9.2 Sampling .............................................................................................................................................. 46 7.9.3 Resampling .......................................................................................................................................... 46 7.9.4 Qualification ......................................................................................................................................... 46 7.9.5 Output Clock Alignment ....................................................................................................................... 46 7.9.6 Frame-Sync Monitor............................................................................................................................. 47 7.9.7 SYNCn Pins ......................................................................................................................................... 47 7.9.8 Other Configuration Options ................................................................................................................ 48 7. ICROPROCESSOR NTERFACE ...
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DS3104-SE Figure 2-1. Typical Application Example ..................................................................................................................... 7 Figure 3-1. Block Diagram ........................................................................................................................................... 8 Figure 7-1. DPLL Block Diagram ............................................................................................................................... 25 Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 27 Figure 7-3. T4 DPLL State Transition Diagram ......................................................................................................... 30 ...
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DS3104-SE Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 14 Table 6-3. Global Pin Descriptions ............................................................................................................................ 15 Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 15 Table ...
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DS3104-SE 1. Standards Compliance Table 1-1. Applicable Telecom Standards SPECIFICATION ANSI T1.101 Synchronization Interface Standard, 1999 TIA/EIA-644-A Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001 ETSI Transmission and Multiplexing (TM); Generic requirements of transport functionality of ...
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DS3104-SE 2. Application Example Figure 2-1. Typical Application Example 4-Port Gigabit Ethernet Line Card Synchronization clock flow only. 10-Gigabit and Fast Ethernet ports and SONET/SDH ports also supported. 125 MHz CMOS/TTL TX GMII GigE to GigE optical RX GMII ...
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DS3104-SE 3. Block Diagram Figure 3-1. Block Diagram IC1 POS/NEG IC2 POS/NEG IC3 IC4 IC5 POS/NEG IC6 POS/NEG IC8 IC9 SYNC1 SYNC2 SYNC3 JTRST JTMS JTAG JTCLK JTDI JTDO 19-4627; Rev 7; 8/10 T4 DPLL (Frequency Conversion) Input PLL ...
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DS3104-SE 4. Detailed Description Figure 3-1 illustrates the blocks described in this section and how they relate to one another. Section detailed feature list. The DS3104- complete line card timing IC for systems with SONET/SDH or Synchronous ...
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DS3104-SE clocks of other frequencies that are phase/frequency locked to the output clock of the associated DPLL. The APLLs multiply the clock rates from the APLL DFS blocks and simultaneously attenuate jitter. Altogether the output blocks of the DS3104-SE ...
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DS3104-SE 5. Detailed Features 5.1 Input Clock Features Eight input clocks: four CMOS/TTL (≤ 125MHz) and four LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz) CMOS/TTL input clocks accept any multiple of 2kHz up to 125MHz LVDS/LVPECL inputs accept any multiple ...
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DS3104-SE 5.4 Output APLL Features Three separate clock-multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates, Fast/Gigabit Ethernet rates and 10G Ethernet rates, all locked to a common reference clock The T0 APLL, always connected to the ...
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DS3104-SE 6. Pin Descriptions Table 6-1. Input Clock Pin Descriptions (1) (2) PIN NAME TYPE Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise local REFCLK I oscillator (XO or TCXO). See Section 7.3. Input Clock 1. LVDS/LVPECL or ...
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DS3104-SE Table 6-2. Output Clock Pin Descriptions (1) (2) PIN NAME TYPE OC1 O Output Clock 1. CMOS/TTL. Programmable frequency (default disabled). OC2 O Output Clock 2. CMOS/TTL. Programmable frequency (default disabled). OC3 O Output Clock 3. CMOS/TTL. Programmable ...
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DS3104-SE Table 6-3. Global Pin Descriptions (1) (2) PIN NAME TYPE Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is reset to default values. The device is held in reset as long as ...
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DS3104-SE Table 6-5. JTAG Interface Pin Descriptions See Section 9 for functional description and Section (1) (2) PIN NAME TYPE JTAG Test Reset (Active Low). Asynchronously resets the test access port (TAP) controller. If JTRST I PU not used, ...
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DS3104-SE 7. Functional Description 7.1 Overview The DS3104-SE has eight input clocks pins and three frame-sync input pins. The device can output as many as nine different clock frequencies on 16 output clock pins. There are two separate DPLLs ...
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DS3104-SE Typically, the internal state machine controls the T0 DPLL, but manual control by system software is also available. The T4 DPLL has a simpler state machine that software cannot directly control. In either DPLL, however, software can override ...
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DS3104-SE 7.4 Input Clock Configuration The DS3104-SE has eight input clocks: IC1 to IC6, IC8, and IC9. each clock, including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks, out to ...
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DS3104-SE 7.4.2 Frequency Configuration Input clock frequencies are configured in the FREQ field of the same registers specify the locking frequency mode, as shown in Table 7-2. Locking Frequency Modes LOCKING FREQUENCY DIVN LOCK8K 0 0 Direct Lock 0 ...
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DS3104-SE 7.5 Input Clock Monitoring Each input clock is continuously monitored for activity. Activity monitoring is described in Sections The valid/invalid state of each input clock is reported in the corresponding real-time status bit in registers or VALSR2. When ...
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DS3104-SE 7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within approximately two missing ...
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DS3104-SE The reference selection algorithm for each DPLL chooses the highest priority valid input clock to be the selected reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table of valid ...
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DS3104-SE in revertive mode, ultra-fast switching could cause excessive reference switching when the highest priority input is intermittent. 7.6.5 External Reference Switching Mode In this mode the SRCSW input pin controls reference switching between two clock inputs. This mode ...
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DS3104-SE 7.7 DPLL Architecture and Configuration Both T0 and T4 are digital PLLs with separate analog PLLs (APLLs) as the output stage. This architecture combines the benefits of both PLL types. See Figure 7-1. DPLL Block Diagram T4 T4 ...
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DS3104-SE Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations, temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers. DPLLs use digital frequency synthesis (DFS) to ...
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DS3104-SE Figure 7-2. T0 DPLL State Transition Diagram (selected reference invalid > 2s [selected reference invalid OR out of lock >100s OR (revertive mode AND valid higher priority input)] AND valid input clock available [selected reference invalid OR (revertive ...
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DS3104-SE 7.7.1.3 Locked State The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.6). ...
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DS3104-SE 7.7.1.6.1 Automatic Holdover For automatic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the ...
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DS3104-SE Figure 7-3. T4 DPLL State Transition Diagram SELECTED REFERENCE SWITCH SELECTED REFERENCE PHASE-LOCKED > 2s SELECTED REFERENCE SWITCH PRELOCKED 2 19-4627; Rev 7; 8/10 RESET FREE-RUN SELECTED REFERENCE SELECTED REFERENCE INACTIVE > 2s ACTIVE PRELOCKED PHASE-LOCKED TO SELECTED ...
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DS3104-SE 7.7.3 Bandwidth The bandwidth of the T4 DPLL is configured in the The bandwidth of the T0 DPLL is configured in the 400Hz. The AUTOBW bit in the MCR9 T0 DPLL uses the T0ABW bandwidth during acquisition (not ...
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DS3104-SE The T0 DPLL phase detectors can be configured for normal phase/frequency locking (360 capture) or nearest edge phase locking (180 capture). With nearest edge detection the phase detectors are immune to occasional missing clock cycles. The DPLL automatically ...
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DS3104-SE When the T4 DPLL declares loss-of-lock, the T4LOCK bit is cleared in the T4LOCK bit in the MSR3 register and requests an interrupt if enabled. 7.7.7 Phase Build-Out 7.7.7.1 Automatic Phase Build-Out in Response to Reference Switching When ...
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DS3104-SE 7.7.10 Frequency and Phase Measurement When the T4 DPLL is not needed to generate an output frequency locked to an input clock, it can measure precise frequency by locking onto any input. It can also measure phase between ...
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DS3104-SE Table 7-5. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode LOCKING MODE LOCKING FOR T4 MODE FOR T0 SELECTED SELECTED REFERENCE REFERENCE LOCK8K or DIRECT DIVN(8K) LOCK8K or LOCK8K DIVN(8K) LOCK8K or DIVN (8K) DIVN(8K) LOCK8K ...
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DS3104-SE 7.7.13 Output Jitter and Wander Several factors contribute to jitter and wander on the output clocks, including: Jitter and wander amplitude on the selected reference (while in the locked state) The jitter/wander transfer characteristic of the ...
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DS3104-SE 7.8 Output Clock Configuration A total of 16 output clock pins, OC1 to OC5, OC1B to OC5B, OC4POS/NEG to OC7POS/NEG, FSYNC, and MFSYNC are available on the device. Output clocks OC1 to OC7 are individually configurable for a ...
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DS3104-SE 7.8.2.1 T0 and T4 DPLL Details See Figure 7-1. The T0 and T4 forward-DFS blocks use the 204.8MHz master clock and DFS technology to synthesize internal clocks from which the output and feedback clocks are derived. The T4 ...
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DS3104-SE 7.8.2.3 OC1 to OC7 Configuration The following is a step-by-step procedure for configuring the frequencies of output clocks OC1 to OC7: 1) Determine whether the T4 APLL must be independent of the T0 DPLL. If the T4 APLL ...
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DS3104-SE Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) APLL APLL / APLL / APLL / FREQUENCY 2 4 312.500 156.250 — 62.500 311.040 155.520 77.760 62.208 274.944 137.472 68.376 250.000 125.000 62.500 50.000 178.944 ...
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DS3104-SE Table 7-12. T4 APLL Frequency Configuration T4 APLL T4 APLL DFS FREQUENCY FREQUENCY (MHz) (MHz) Disabled 77.76 311.04 77.76 98.304 24.576 131.072 32.768 148.224 37.056 98.816 24.704 274.944 68.736 178.944 44.736 100.992 25.248 250.000 62.500 122.88 30.720 160.000 ...
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DS3104-SE Table 7-14. Standard Frequencies for Programmable Outputs FREQUENCY (MHz) 2kHz 8kHz 1.536 Not OC4, OC5 from T4 APLL Not OC4–OC7 from T0 APLL 1.544 Not OC6 from DIG2 1.544 Not OC4, OC5 from T4 APLL Not OC4–OC7 from ...
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DS3104-SE FREQUENCY (MHz) 16.000 Not OC6, OC7 16.384 Not OC6 from DIG2 16.384 16.384 16.832 17.184 18.528 19.440 Not OC6 19.440 20.000 20.800 OC2, OC3, OC6, OC7 only 22.368 24.576 24.576 OC2, OC3, OC6, OC7 only 24.704 24.704 25.000 ...
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DS3104-SE FREQUENCY (MHz) 122.880 OC6, OC7 only 125.000 Not OC1–OC3 from T0 APLL Not OC1, OC2 from T4 APLL 131.072 Not OC1–OC3 from T0 APLL OC6, OC7 only from T4 APLL 137.472 OC6, OC7 only 148.224 Not OC1–OC3 from ...
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DS3104-SE 7.8.2.5 Custom Output Frequencies In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be configured to generate a custom frequency. Possible custom frequencies include any multiple of 2kHz ...
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DS3104-SE Table 7-15. External Frame-Sync Mode and Source T0 DPLL MCR3: FSCR3: 1 LOCKED EFSEN SOURCE XXXX 1 0 XXXX 1 1 <>11XX 1 1 <>11XX 1 1 11XX Note 1: That is, when OPSTATE:T0STATE=100. Note ...
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DS3104-SE signal is qualified, the FSYNC/MFSYNC 2kHz alignment generator is always synchronized by SYNCn, and, therefore, FSYNC and MFSYNC are always falling-edge aligned with SYNCn. When FSCR2:INDEP = 0, the T0 DPLL 2kHz alignment generator is also synchronized with ...
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DS3104-SE 7.9.8 Other Configuration Options FSYNC and MFSYNC are always produced from the T0 DPLL. Output clocks OC1 to OC7 can also be configured as 2kHz or 8kHz outputs, derived from either the T0 DPLL or the T4 DPLL ...
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DS3104-SE the data on SDO, increment its address counter, and prefetch the following byte. After the address counter reaches 3FFFh, it rolls over to address 0000h and continues to increment. Early Termination of Bus Transactions. The bus master can ...
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DS3104-SE Figure 7-6. SPI Bus Transactions Single-Byte Write CS R/W Register Address Burst SDI 0 (Write) SDO Single-Byte Read CS R/W Register Address Burst SDI 1 (Read) SDO Burst Write CS R/W Register Address Burst Data Byte 1 SDI ...
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DS3104-SE 7.11 Reset Logic The device has three reset controls: the RST pin, the RST bit in MCR1, and the JTAG reset pin JTRST. The RST pin asynchronously resets the entire device, except for the JTAG logic. When the ...
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DS3104-SE 8. Register Descriptions The DS3104-SE has an overall address range from 000h to 1FFh. In each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are reserved ...
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DS3104-SE 8.4 Register Definitions Table 8-1. Register Map Note: Register names are hyperlinks to register definitions. Underlined fields are read-only. ADDR REGISTER BIT 7 00h ID1 01h ID2 02h REV 03h TEST1 PALARM 05h MSR1 IC8 06h MSR2 STATE ...
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DS3104-SE ADDR REGISTER BIT 7 3Ah MCR8 OC5SF 3Bh MCR9 AUTOBW 3Ch MCLK1 3Dh MCLK2 40h HOCR3 AVG 41h DLIMIT1 42h DLIMIT2 — 43h IER1 IC8 44h IER2 STATE SRFAIL 45h IER3 FSMON T4LOCK 46h DIVN1 47h DIVN2 48h ...
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DS3104-SE ADDR REGISTER BIT 7 72h PBOFF — 73h PHLIM1 FLEN NALOL 74h PHLIM2 CLEN MCPDEN USEMCPD 76h PHMON NW 77h PHASE1 78h PHASE2 79h PHLKTO PHLKTOM[1:0] 7Ah FSCR1 2K8KSRC 7Bh FSCR2 INDEP 7Ch FSCR3 RECAL 7Dh INTCR — ...
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DS3104-SE Register Name: ID1 Register Description: Device Identification Register, LSB Register Address: 00h Bit # 7 6 Name Default 0 0 Bits Device ID (ID[7:0]). ID[15:0] = 0C20h = 3104 decimal. Register Name: ID2 Register Description: ...
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DS3104-SE Register Name: TEST1 Register Description: Test Register 1 (Not Normally Used) Register Address: 03h Bit # 7 6 Name PALARM D180 Default 0 0 Bit 7: Phase Alarm (PALARM). This real-time status bit indicates the state of the ...
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DS3104-SE Register Name: MSR1 Register Description: Master Status Register 1 Register Address: 05h Bit # 7 6 Name IC8 — Default 1 0 Bits 7 and Input Clock Status Change (IC8 and IC[6:1]). Each of these ...
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DS3104-SE Register Name: MSR3 Register Description: Master Status Register 3 Register Address: 08h Bit # 7 6 Name FSMON T4LOCK Default 0 1 Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This latched status bit is set to 1 when ...
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DS3104-SE Register Name: OPSTATE Register Description: Operating State Register Register Address: 09h Bit # 7 6 Name FSMON T4LOCK Default 1 0 Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This real-time status bit indicates the current status of the ...
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DS3104-SE Register Name: PTAB1 Register Description: Priority Table Register 1 Register Address: 0Ah Bit # 7 6 Name REF1[3:0] Default 0 0 Bits Highest Priority Valid Reference (REF1[3:0]). This real-time status field indicates the highest priority ...
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DS3104-SE Register Name: PTAB2 Register Description: Priority Table Register 2 Register Address: 0Bh Bit # 7 6 Name REF3[3:0] Default 0 0 Bits Third Highest Priority Valid Reference (REF3[3:0]). This real-time status field indicates the third ...
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DS3104-SE Register Name: FREQ1 Register Description: Frequency Register 1 Register Address: 0Ch Bit # 7 6 Name Default 0 0 Note: The FREQ1, FREQ2, and FREQ3 registers must be read consecutively. See Section 8.3. Bits Current ...
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DS3104-SE Register Name: VALSR1 Register Description: Input Clock Valid Status Register 1 Register Address: 0Eh Bit # 7 6 Name IC8 — Default 0 0 Bits 7 and Input Clock Valid Status (IC8 and IC[6:1]). Each ...
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DS3104-SE Register Name: ISR1 Register Description: Input Status Register 1 Register Address: 10h Bit # 7 6 Name — — Default 0 0 Bit 5: Activity Alarm for Input Clock 2 (ACT2). This real-time status bit is set to ...
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DS3104-SE Register Name: ISR3 Register Description: Input Status Register 3 Register Address: 12h Bit # 7 6 Name — — Default 0 0 This register has the same behavior as the ISR1and Register Name: ISR4 Register Description: Input Status ...
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DS3104-SE Register Name: MSR4 Register Description: Master Status Register 4 Register Address: 17h Bit # 7 6 Name — HORDY Default 0 0 Bit 6: Holdover Frequency Ready (HORDY). This latched status bit is set to 1 when the ...
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DS3104-SE Register Name: IPR1 Register Description: Input Priority Register 1 Register Address: 18h Bit # 7 Name Default (T0) 0 Default (T4) 0 Bits Priority for Input Clock 2 (PRI2[3:0]). Priority 0001 is highest; priority 1111 ...
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DS3104-SE Register Name: IPR3 Register Description: Input Priority Register 3 Register Address: 1Ah Bit # 7 Name Default (T0) 0 Default (T4) 0 These registers have the same behavior as Register Name: IPR4 Register Description: Input Priority Register 4 ...
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DS3104-SE Register Name: ICR1, ICR2, ICR3, ICR4, ICR5, ICR6, ICR8, ICR9 Register Description: Input Configuration Register Register Address: 20h, 21h, 22h, 23h, 24h, 25h, 27h, 28h Bit # 7 6 Name ...
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DS3104-SE DIVN = 1 and LOCK8K = 1: (Alternate direct-lock frequency decode) 0000 = 10MHz (internally divided down to 5MHz) 0001 = 25MHz (internally divided down to 5MHz) 0010 = 62.5MHz (internally down to 31.25MHz) 0011 = 125MHz (internally ...
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DS3104-SE Register Name: MCR1 Register Description: Master Configuration Register 1 Register Address: 32h Bit # 7 6 Name RST — Default 0 0 Bit 7: Device Reset (RST). When this bit is high the entire device is held in ...
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DS3104-SE Register Name: MCR2 Register Description: Master Configuration Register 2 Register Address: 33h Bit # 7 6 Name — — Default 0 0 Bits DPLL Force Selected Reference (T0FORCE[3:0]). This field provides a way to ...
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DS3104-SE Register Name: MCR3 Register Description: Master Configuration Register 3 Register Address: 34h Bit # 7 6 Name AEFSEN LKATO Default 1 1 Bit 7: Auto External Frame Sync Enable (AEFSEN). This bit has two functions depending on the ...
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DS3104-SE Register Name: MCR4 Register Description: Master Configuration Register 4 Register Address: 35h Bit # 7 6 Name LKT4T0 — Default 0 0 Bit 7: Lock (LKT4T0). When this bit is set to 1 (and T0CR1:T4APT0 ...
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DS3104-SE Register Name: MCR5 Register Description: Master Configuration Register 5 Register Address: 36h Bit # 7 6 Name RSV4 RSV3 Default 0 0 Bits Reserved Bit (RSV[4:1]). These bits are reserved for future ...
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DS3104-SE Register Name: OCR6 Register Description: Output Configuration Register 6 Register Address: 37h Bit # 7 6 Name — OC5EN Default 0 1 Bit 6: OC5 Output Enable (OC5EN). Enables the OC5 output pin Output clock pin ...
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DS3104-SE Register Name: MCR6 Register Description: Master Configuration Register 6 Register Address: 38h Bit # 7 6 Name DIG2AF DIG2SS Default 0 see below Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies Digital2 ...
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DS3104-SE Register Name: MCR7 Register Description: Master Configuration Register 7 Register Address: 39h Bit # 7 6 Name DIG2F[1:0] Default 0 0 Bits Digital2 Frequency (DIG2F[1:0]). This field, MCR6:DIG2SS, and MCR6:DIG2AF configure the frequency of the ...
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DS3104-SE Register Name: MCR8 Register Description: Master Configuration Register 8 Register Address: 3Ah Bit # 7 6 Name OC5SF[1:0] Default 0 0 For Rev A2 devices, in LVPECL mode the differential output voltage will be higher than the MAX ...
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DS3104-SE Register Name: MCR9 Register Description: Master Configuration Register 9 Register Address: 3Bh Bit # 7 6 Name AUTOBW — Default 1 1 Bit 7: Automatic Bandwidth Selection (AUTOBW). See Section 7.7. Always selects locked bandwidth from ...
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DS3104-SE Register Name: MCLK1 Register Description: Master Clock Frequency Adjustment Register 1 Register Address: 3Ch Bit # 7 6 Name Default 1 0 Note: The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See Section 8.3. ...
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DS3104-SE Register Name: DLIMIT1 Register Description: DPLL Frequency Limit Register 1 Register Address: 41h Bit # 7 6 Name Default 0 1 Note: The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3. Bits ...
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DS3104-SE Register Name: IER1 Register Description: Interrupt Enable Register 1 Register Address: 43h Bit # 7 6 Name IC8 — Default 0 0 Bits 7 and Interrupt Enable for Input Clock Status Change (IC8 and IC[6:1]). ...
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DS3104-SE Register Name: IER3 Register Description: Interrupt Enable Register 3 Register Address: 45h Bit # 7 6 Name FSMON T4LOCK Default 0 0 Bit 7: Interrupt Enable for Frame-Sync Input Monitor Alarm (FSMON). This bit is an interrupt enable ...
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DS3104-SE Register Name: DIVN1 Register Description: DIVN Register 1 Register Address: 46h Bit # 7 6 Name Default 1 1 Note: The DIVN1 and DIVN2 registers must be read consecutively and written consecutively. See Section 8.3. Bits 7 to ...
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DS3104-SE Register Name: MCR10 Register Description: Master Configuration Register 10 Register Address: 48h Bit # 7 6 Name — SRFPIN Default 1 0 Bit 6: SRFAIL Pin Enable (SRFPIN). When this bit is set to 1, the SRFAIL pin ...
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DS3104-SE Register Name: DLIMIT3 Register Description: DPLL Frequency Limit Register 3 Register Address: 4Dh Bit # 7 6 Name FLLOL Default 1 0 Bit 7: Frequency Limit Loss-of-Lock (FLLOL). When this bit is set to 1, the T0 DPLL ...
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DS3104-SE Register Name: OCR5 Register Description: Output Configuration Register 1 Register Address: 4Fh Bit # 7 6 Name — AOF7 Default 0 0 Bit 6: Alternate Output Frequency Mode Select 7 (AOF7). This bit controls the decoding of the ...
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DS3104-SE Register Name: LB0U Register Description: Leaky Bucket 0 Upper Threshold Register Register Address: 50h Bit # 7 6 Name Default 0 0 Bits Leaky Bucket 0 Upper Threshold (LB0U[7:0]). When the leaky bucket accumulator is ...
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DS3104-SE Register Name: LB1U, LB2U, LB3U Register Description: Leaky Bucket 1/2/3 Upper Threshold Register Register Address: 54h, 58h, 5Ch Bit # 7 6 Name Default 0 0 Bits Leaky Bucket “x” Upper Threshold (LBxU[7:0]). See the ...
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DS3104-SE Register Name: OCR1 Register Description: Output Configuration Register 1 Register Address: 60h Bit # 7 6 Name OFREQ2[3:0] Default 0 0 Bits Output Frequency of OC2 (OFREQ2[3:0]). This field specifies the frequency of output clock ...
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DS3104-SE 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 64 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided ...
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DS3104-SE Register Name: OCR2 Register Description: Output Configuration Register 2 Register Address: 61h Bit # 7 6 Name OFREQ4[3:0] Default 0 0 Bits Output Frequency of OC4 (OFREQ4[3:0]). This field specifies the frequency of output clock ...
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DS3104-SE 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 64 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided ...
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DS3104-SE Register Name: OCR3 Register Description: Output Configuration Register 3 Register Address: 62h Bit # 7 6 Name OFREQ6[3:0] Default 0 0 Bits Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock ...
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DS3104-SE 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 2 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided ...
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DS3104-SE Register Name: OCR4 Register Description: Output Configuration Register 4 Register Address: 63h Bit # 7 6 Name MFSEN FSEN Default 1 1 Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2kHz output on the MFSYNC pin. ...
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DS3104-SE Register Name: T4CR1 Register Description: T4 DPLL Configuration Register 1 Register Address: 64h Bit # 7 6 Name — — Default 0 0 Bits APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0 = 0, the T4 APLL ...
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DS3104-SE Register Name: T0CR1 Register Description: T0 DPLL Configuration Register 1 Register Address: 65h Bit # 7 6 Name T4MT0 T4APT0 Default 0 1 Bit 7: T4 Measure T0 Phase (T4MT0). When this bit is set to 1 the ...
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DS3104-SE Register Name: T4BW Register Description: T4 Bandwidth Register Register Address: 66h Bit # 7 6 Name 0 0 Default 0 0 Bits DPLL Bandwidth (T4BW[2:0]). See Section 7.7. 18Hz 01 = 35Hz ...
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DS3104-SE Register Name: T0ABW Register Description: T0 DPLL Acquisition Bandwidth Register Register Address: 69h Bit # 7 6 Name — — Default 0 0 Bit 4: Reserved Bit 1 (RSV1). This bit is reserved for future use, it can ...
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DS3104-SE Register Name: T4CR2 Register Description: T4 Configuration Register 2 Register Address: 6Ah Bit # 7 6 Name — Default 0 0 Bits Phase Detector 2 Gain 8kHz (PD2GA8K[2:0]). This field specifies the gain of the ...
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DS3104-SE Register Name: T0CR2 Register Description: T0 Configuration Register 2 Register Address: 6Bh Bit # 7 6 Name — Default 0 0 Bits Phase Detector 2 Gain, 8kHz (PD2G8K[2:0]). This field specifies the gain of the ...
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DS3104-SE Register Name: T4CR3 Register Description: T4 Configuration Register 3 Register Address: 6Ch Bit # 7 6 Name PD2EN Default 1 1 Bit 7: Phase Detector 2 Gain Enable (PD2EN). When this bit is set to 1, the T4 ...
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DS3104-SE Register Name: GPCR Register Description: GPIO Configuration Register Register Address: 6Eh Bit # 7 6 Name GPIO4D GPIO3D Default 0 0 Bit 7: GPIO4 Direction (GPIO4D). This bit configures the data direction for the GPIO4 pin. When GPIO4 ...
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DS3104-SE Register Name: GPSR Register Description: GPIO Status Register Register Address: 6Fh Bit # 7 6 Name — — Default 0 0 Bit 3: GPIO4 State (GPIO4). This bit indicates the current state of the GPIO4 pin ...
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DS3104-SE Register Name: OFFSET1 Register Description: Phase Offset Register 1 Register Address: 70h Bit # 7 6 Name Default 0 0 Note: The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutively. See Section 8.3. Bits 7 ...
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DS3104-SE Register Name: PBOFF Register Description: Phase Build-Out Offset Register Register Address: 72h Bit # 7 6 Name — — Default 0 0 Bits Phase Build-Out Offset Register (PBOFF[5:0]). An uncertainty 5ns is ...
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DS3104-SE Register Name: PHLIM2 Register Description: Phase Limit Register 2 Register Address: 74h Bit # 7 6 Name CLEN MCPDEN Default 1 0 Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified ...
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DS3104-SE Register Name: PHMON Register Description: Phase Monitor Register Register Address: 76h Bit # 7 6 Name NW — Default 0 0 Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kHz, or 8kHz input clocks, this configuration ...
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DS3104-SE Register Name: PHASE1 Register Description: Phase Register 1 Register Address: 77h Bit # 7 6 Name Default 0 0 Note: The PHASE1 and PHASE2 registers must be read consecutively. See Section 8.3. Bits Current DPLL ...
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DS3104-SE Register Name: FSCR1 Register Description: Frame-Sync Configuration Register 1 Register Address: 7Ah Bit # 7 6 Name 2K8KSRC Default 0 0 Bit 7: 2kHz/8kHz Source (2K8KSRC). This configuration bit specifies the source for the 2kHz and 8kHz outputs ...
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DS3104-SE Register Name: FSCR2 Register Description: Frame-Sync Configuration Register 2 Register Address: 7Bh Bit # 7 6 Name INDEP OCN Default 0 0 Bit 7: Independent Frame Sync and Multiframe Sync (INDEP). When this bit is set to 0, ...
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DS3104-SE Register Name: FSCR3 Register Description: Frame-Sync Configuration Register 3 Register Address: 7Ch Bit # 7 6 Name RECAL Default 0 0 Bit 7: Phase Offset Recalibration (RECAL). When set to 1, this configuration bit causes a recalibration of ...
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DS3104-SE Register Name: INTCR Register Description: Interrupt Configuration Register Register Address: 7Dh Bit # 7 6 Name — — Default 0 0 Bit 3: INTREQ Pin Mode (LOS). When GPO = 0, this bit selects the function of the ...
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DS3104-SE 9. JTAG Test Access Port and Boundary Scan 9.1 JTAG Description The DS3104-SE supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. contains the following items, which meet the ...
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DS3104-SE 9.2 JTAG TAP Controller State Machine Description This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge ...
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DS3104-SE Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR. ...
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DS3104-SE 9.3 JTAG Instruction Register and Instructions The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register ...
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DS3104-SE 9.4 JTAG Test Registers IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An optional test register, the identification register, has been included in the device design used with ...
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DS3104-SE 10. Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin with Respect to V Supply Voltage Range (V ) with Respect Supply Voltage Range (V ) with Respect to V DDIO Ambient Operating Temperature ...
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DS3104-SE Table 10-3. CMOS/TTL Pins = 1.8V 10 3.3V 5 DDIO PARAMETER Input High Voltage Input Low Voltage Input Leakage Input Leakage, Pins with Internal Pullup Resistor (50k typ) Input Leakage, Pins with Internal ...
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DS3104-SE Table 10-6. LVPECL Level-Compatible Output Pins = 1.8V 10 3.3V 5 DDIO PARAMETER Differential Output Voltage Output Offset (Common Mode) Voltage Difference in Magnitude of Output Differential Voltage for Complementary States With 100 ...
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DS3104-SE Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins DS3104 LVPECL LEVEL- COMPATIBLE OUTPUTS 19-4627; Rev 7; 8/10 3.3V 82 82 50 OCnPOS 0.01F 50 OCnNEG 130 130 GND LVPECL RECEIVER 125 of 136 ...
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DS3104-SE 10.2 Input Clock Timing Table 10-7. Input Clock Timing = 1.8V 10 3.3V 5 DDIO PARAMETER CMOS/TTL Input Pins Input Clock Period LVDS/LVPECL Input Pins Input Clock High, Low Time 10.3 Output Clock ...
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DS3104-SE 10.4 SPI Interface Timing Table 10-10. SPI Interface Timing = 1.8V 10 3.3V 5 DDIO PARAMETER (Note 1) SCLK Frequency SCLK Cycle Time CS Setup to First SCLK Edge CS Hold Time After ...
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DS3104-SE Figure 10-4. SPI Interface Timing Diagram CPHA = SUC CYC SCLK, CPOL=0 t CLKH t SCLK, CLKL CPOL SUI HDI SDI SDO CPHA = SUC CYC SCLK, CPOL=0 ...
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DS3104-SE 10.5 JTAG Interface Timing Table 10-11. JTAG Interface Timing = 1.8V 10 3.3V 5 DDIO PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time (Note 1) JTCLK to JTDI, JTMS Setup Time JTCLK to ...
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DS3104-SE 10.6 Reset Pin Timing Table 10-12. Reset Pin Timing = 1.8V 10 3.3V 5 DDIO PARAMETER RST Low Time (Note 1) SONSDH, SRCSW Setup Time to RST SONSDH, SRCSW Hold Time from RST ...
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DS3104-SE 11. Pin Assignments Table 11-1 lists pin assignments sorted in alphabetical order by pin name. arranged by pin number. Table 11-1. Pin Assignments Sorted by Signal Name PIN NAME PIN NUMBER AVDD_PLL1 B2 AVDD_PLL2 C2 AVDD_PLL3 F2 AVDD_PLL4 ...
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DS3104-SE Figure 11-1. Pin Assignment Diagram AVSS_PLL1 TEST INTREQ/ B AVDD_PLL1 LOS C REFCLK AVDD_PLL2 AVSS_PLL2 D OC4NEG OC4POS E OC5NEG OC5POS F AVSS_PLL3 AVDD_PLL3 AVDD_PLL4 G SRCSW AVSS_PLL4 H FSYNC OC6POS J MFSYNC OC6NEG High-Speed ...
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DS3104-SE 12. Package Information For the latest package outline information and land patterns www.maxim-ic.com/packages. “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains ...
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DS3104-SE 13. Acronyms and Abbreviations AIS Alarm Indication Signal AMI Alternate Mark Inversion APLL Analog Phase-Locked Loop BITS Building Integrated Timing Supply BPV Bipolar Violation DFS Digital Frequency Synthesis DPLL Digital Phase-Locked Loop ESF Extended Superframe EXZ Excessive Zeros ...
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DS3104-SE 14. Data Sheet Revision History REVISION REVISION NUMBER DATE 0 060507 Initial data sheet release. Corrected typo in Features bullet, Programmable PLL Bandwidth, from 1Hz to 0.1Hz 1 070507 (0.1Hz to 400Hz). Added reference to G.8262 to In ...
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... SRFAIL pin description to indicate state is high impedance when 7.7.6 deleted sentence that said the hard and soft limits have hysteresis. Maxim is a registered trademark of Maxim Integrated Products. PAGES CHANGED 45, 46, 47, 74, 113, 115 ...