DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 33

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

________________________________________________________________________________________ DS3104-SE
When the T4 DPLL declares loss-of-lock, the T4LOCK bit is cleared in the
OPSTATE
register, which sets the
T4LOCK bit in the
MSR3
register and requests an interrupt if enabled.
7.7.7 Phase Build-Out
7.7.7.1 Automatic Phase Build-Out in Response to Reference Switching
When MCR10:PBOEN = 0, phase build-out is not performed during reference switching. The T0 DPLL always
locks to the selected reference at zero degrees of phase. With PBO disabled, transitions from a failed reference to
the next highest priority reference and transitions from holdover or free-run to locked mode cause phase transients
on output clocks as the T0 DPLL jumps from its previous phase to the phase of the new selected reference.
When MCR10:PBOEN = 1, phase build-out is performed during reference switching (or exiting from holdover). With
PBO enabled, if the selected reference fails and another valid reference is available, the device enters a temporary
holdover state in which the phase difference between the new reference and the output is measured and fed into
the DPLL loop to absorb the input phase difference. Similarly, during transitions from full-holdover, mini-holdover,
or free-run to locked mode, the phase difference between the new reference and the output is measured and fed
into the DPLL loop to absorb the input phase difference. After a PBO event, regardless of the input phase
difference, the output phase transient is less than or equal to 5ns.
Any time that PBO is enabled it can also be frozen at the current phase offset by setting MCR10:PBOFRZ = 1.
When PBO is frozen, the T0 DPLL ignores subsequent phase build-out events and maintains the current phase
offset between inputs and outputs.
Disabling PBO while the T0 DPLL is not in the free-run or holdover states (locking or locked) causes a phase
change on the output clocks while the DPLL switches to tracking the selected reference with zero degrees of phase
error. The rate of phase change on the output clocks depends on the DPLL bandwidth. Enabling PBO (which
includes unfreezing) while locking or locked also causes a PBO event.
7.7.7.2 PBO Phase Offset Adjustment
An uncertainty of up to 5ns is introduced each time a phase build-out event occurs. This uncertainty results in a
phase hit on the output. Over a large number of phase build-out events the mean error should be zero. The
PBOFF
register specifies a small fixed offset for each phase build-out event to skew the average error toward zero and
eliminate accumulation of phase shifts in one direction.
7.7.8 Input to Output (Manual) Phase Adjustment
When phase build-out is disabled (PBOEN = 0 in MCR10), the
OFFSET
registers can be used to adjust the phase
of the T0 DPLL output clocks with respect to the selected reference when locked. Output phase offset can be
adjusted over a 200ns range in 6ps increments. This phase adjustment occurs in the feedback clock so that the
output clocks are adjusted to compensate. The rate of change is therefore a function of DPLL bandwidth. Simply
writing to the
OFFSET
registers with phase build-out disabled causes a change in the input to output phase, which
can be considered to be a delay adjustment. Changing the OFFSET adjustment while in free-run or holdover state
does not cause an output phase offset until it exits the state and enters one of the locking states.
7.7.9 Phase Recalibration
When a phase buildout occurs, either automatic or manual, the feedback frequency synthesizer does not get an
internal alignment signal to keep it aligned with the output dividers, and therefore the phase difference between
input and output can become incorrect. Setting the FSCR3:RECAL bit periodically causes a recalibration process
to be executed, which corrects any phase error that may have occurred.
During the recalibration process the device puts the DPLL into mini-holdover, internally ramps the phase offset to
zero, resets all clock dividers, ramps the phase offset to the value stored in the
OFFSET
registers, and switches
the DPLL out of mini-holdover. If the
OFFSET
registers are written during the recalibration process, the process
ramps the phase offset to the new offset value.
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