DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 82

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[7:0]). The full 16-bit MCLKFREQ[15:0] field
spans this register and
204.8MHz master clock with respect to the frequency of the local oscillator clock on the REFCLK pin by up to
+514ppm and -771ppm. The master clock adjustment has the effect of speeding up the master clock with a positive
adjustment and slowing it down with a negative adjustment. For example, if the oscillator connected to REFCLK
has an offset of +1ppm, the adjustment should be -1ppm to correct the offset.
The formulas below translate adjustments to register values and vice versa. The default register value of 39,321
corresponds to 0ppm. See Section 7.3.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[15:8]). See the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See Section
Bit 7: Averaging (AVG). When this bit is set to 1 the T0 DPLL uses the averaged frequency value during holdover
mode. When FRUNHO = 1 in the
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
MCLKFREQ[15:0] = adjustment_in_ppm / 0.0196229 + 39,321
adjustment_in_ppm = (MCLKFREQ[15:0] – 39,321)  0.0196229
0 = Not averaged frequency; holdover frequency is either free-run (FRUNHO = 1) or instantaneously
1 = Averaged frequency over the last one second while locked to the input.
frozen.
8.3
AVG
7
1
7
1
7
1
for important information about writing and reading this register.
MCLK2.
—
6
0
6
0
6
0
MCR3
MCLK1
Master Clock Frequency Adjustment Register 1
3Ch
MCLK2
Master Clock Frequency Adjustment Register 2
3Dh
HOCR3
Holdover Configuration Register 3
40h
MCLKFREQ is an unsigned integer that adjusts the frequency of the internal
register, this bit is ignored. See Section 7.7.1.6.
—
5
0
5
0
5
0
MLCKFREQ[15:8]
MCLKFREQ[7:0]
—
4
1
4
1
4
0
—
3
1
3
1
3
1
—
MCLK1
2
0
2
0
2
0
register description.
—
1
0
1
0
1
0
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—
0
1
0
1
0
0