DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 29

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

________________________________________________________________________________________ DS3104-SE
7.7.1.6.1 Automatic Holdover
For automatic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or
averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the DPLL’s current
frequency 50ms to 100ms before entry into holdover (i.e., the value of the FREQ field in the FREQ1, FREQ2, and
FREQ3
registers when MCR11:T4T0 = 0). The FREQ field is the DPLL’s integral path and, therefore, is an average
frequency with a rate of change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not
used in order to minimize the effect of recent phase disturbances on the holdover frequency.
In averaged mode (AVG = 1 in
HOCR3
and FRUNHO = 1 in MCR3), the holdover frequency is set to an internally
averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged over a
one-second period. The T0 DPLL indicates that it has acquired a valid holdover value by setting the HORDY status
bit in
VALSR2
(real-time status) and
MSR4
(latched status). If the T0 DPLL must enter holdover before the
one-second average is available, an instantaneous value 50ms to 100ms old from the integral path is used instead.
7.7.1.6.2 Free-Run Holdover
For free-run holdover (FRUNHO = 1 in MCR3), the output frequency accuracy is generated with the accuracy of
the external oscillator frequency. The actual frequency is the frequency of the external oscillator plus the value of
the MCLK offset specified in the MCLKFREQ field in registers
MCLK1
and
MCLK2
(see Section 7.3). When
MCR3.FRUNHO is set the HOCR3:AVG bit is ignored.
7.7.1.7 Mini-Holdover
When the selected reference fails, the fast activity monitor (Section 7.5.3) isolates the T0 DPLL from the reference
within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation occurs, the
DPLL enters a temporary mini-holdover mode, with a frequency equal to an instantaneous value 50ms to 100 ms
old from the integral path of the loop filter. Mini-holdover lasts until the selected reference becomes active or the
state machine enters the holdover state. If the free-run holdover mode is set (FRUNHO = 1 in MCR3), the mini-
holdover frequency accuracy is exactly the same as the external oscillator accuracy plus the offset set by the
MCLKFREQ field in registers
MCLK1
and
MCLK2
(see Section 7.3).
7.7.2 T4 DPLL State Machine
The T4 DPLL state machine is similar to the T0 DPLL, as shown in
Figure
7-3. The T4 DPLL states are similar to
the equivalent states of the T0 DPLL, but the only state indicator is the T4LOCK bit in the
OPSTATE
register. Note
that the T4 DPLL only operates in revertive switching mode. The full-holdover and mini-holdover modes are
instantaneous (see the first paragraph of Section 7.7.1.6.1).
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