DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 135
DS3104GN
Manufacturer Part Number
DS3104GN
Description
Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3104GN.pdf
(136 pages)
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14.
19-4627; Rev 6; 5/09
________________________________________________________________________________________ DS3104-SE
REVISION
NUMBER
0
1
2
3
Data Sheet Revision History
REVISION
060507
070507
071807
110207
DATE
Initial data sheet release.
Corrected typo in Features bullet, Programmable PLL Bandwidth, from 1Hz to 0.1Hz
(0.1Hz to 400Hz).
Added reference to G.8262 to
In the OC3B pin description in
OC3BEN.
In
pin description to clarify its non-INTREQ function.
In
power supply for T0 APLL2 rather than T0 APLL.
In Section 7.11, emphasized the need for RST pin assertion and added requirement to
least 100µs after reset is deasserted before initializing the device.
In the MSR2:SRFAIL bit description, deleted references to the INTREQ/SRFAIL pin
and to INTCR:SRFAIL.
In the
“T4DIGFB” to “—“.
Deleted reference to nonexistent PMPBEN bit in the
Changed INTCR:SRFAIL to LOS and changed its bit description to clarify function.
Updated references to this bit in other INTCR bit descriptions.
In
In
Added that custom output frequencies are also available for any multiple of 10kHz up
to 388.79MHz.
Updated most of the typical jitter numbers in
data.
Edited the text of Section
Added text and procedure related to LVPECL mode to the
in MCR8, added text to clarify that the 00 decode for each field powers down the
output.
Added “1000 = T0 selected reference” option to the OFREQ1 to OFREQ7 fields in the
OCR
In
185mA to 192mA, changed I
from 45mA to 52mA to reflect the power consumption of rev A2. Also added a
clarification to Note 3 to define what “enabled” means.
In
+85A to +100A to reflect the slightly higher leakage current of rev A2.
Table
Table
Table
Figure
Table
Table 10-3
registers.
MCR4
6-3, changed pin name INTREQ/SRFAIL to INTREQ/LOS and changed the
6-6, corrected AVDD_PLL4 and AVSS_PLL4 descriptions to say they are the
11-1, changed INTREQ to INTREQ/LOS.
10-2, changed I
11-1, changed INTREQ to INTREQ/LOS.
register description header, corrected typo by renaming bit 6 from
, changed I
DD
7.12
ILPU
typical from 160mA to 153mA, changed I
DDIO
min from -85A to -100A and changed I
Table
Table
for clarity.
typical from 29mA to 41mA, and changed I
DESCRIPTION
1-1.
6-2, corrected typo by changing OC2BEN to
Table 7-14
OFFSET1
from Rev A2 characterization
MCR8
register.
register description;
DD
ILPD
max from
max from
DDIO
max
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1, 12
107
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15
16
52
58
75
42
51
80
—
1
6
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