DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 111

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kHz, or 8kHz input clocks, this configuration
bit enables a 5% tolerance noise window centered around the expected clock edge location. Noise-induced edges
outside this window are ignored, reducing the possibility of phase hits on the output clocks. This only applies to the
T0 DPLL and should be enabled only when the T0 DPLL is locked to an input and the 180 phase detector is being
used
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
(TEST1.D180=0)
0 = All edges are recognized by the T0 DPLL.
1 = Only edges within the 5% tolerance window are recognized by the T0 DPLL.
NW
7
0
.
—
6
0
PHMON
Phase Monitor Register
76h
—
5
0
—
4
0
—
3
0
—
2
1
—
1
1
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—
0
0