DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 22

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity
monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within
approximately two missing reference clock cycles (approximately four missing cycles for 156.25MHz, 155.52MHz,
125MHz, 62.5MHz, 25MHz, and 10MHz references).
When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the
selected reference and sets the SRFAIL bit in MSR2. The setting of the SRFAIL bit can cause an interrupt request
if the corresponding enable bit is set in IER2. If MCR10:SRFPIN = 1, the SRFAIL output pin follows the state of the
SRFAIL status bit. Optionally, a no-activity event can also cause an ultra-fast reference switch (see Section 7.6.4).
When PHLIM1:NALOL = 0 (default), the T0 DPLL does not declare loss-of-lock during no-activity events. If the
selected reference becomes available again before any alarms are declared by the activity monitor, the T0 DPLL
continues to track the selected reference using nearest edge locking (180) to avoid cycle slips. When NALOL =
1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the T0 DPLL state machine to transition
to the loss-of-lock state, which sets the MSR2:STATE bit and causes an interrupt request if enabled. If the selected
reference becomes available again before any alarms are declared by the activity monitor, the T0 DPLL tracks the
selected reference using phase/frequency locking (360) until phase lock is reestablished.
When the T4 DPLL detects a no-activity event, its behavior is similar to the T0 DPLL with respect to the
PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If
NALOL = 1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an
interrupt request if enabled.
7.6
7.6.1 Priority Configuration
During normal operation, the selected reference for the T0 DPLL and the selected reference for the T4 DPLL are
chosen automatically based on the priority rankings assigned to the input clocks in the input priority registers
to IPR5). Each of these registers has priority fields for one or two input clocks. When T4T0 = 0 in the
register, the IPR registers specify the input clock priorities for the T0 DPLL. When T4T0 = 1, the IPR registers
specify the input clock priorities for the T4 DPLL. The default input clock priorities, for both PLLs, are shown in
Table
Any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable
for selection. Priority 1 is highest while priority 15 is lowest. The same priority can be given to two or more clocks.
Table 7-3. Default Input Clock Priorities
7.6.2 Automatic Selection Algorithm
The real-time valid/invalid state of each input clock is maintained in the
selected reference can be marked invalid for phase lock, frequency, or activity. Other input clocks can be
invalidated for frequency or activity.
19-4627; Rev 7; 8/10
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INPUT CLOCK
7-3.
IC1
IC2
IC3
IC4
IC5
IC6
IC8
IC9
Input Clock Priority, Selection, and Switching
DEFAULT
PRIORITY
T0 DPLL
0 (off)
0 (off)
0 (off)
1
2
3
4
5
DEFAULT
PRIORITY
T4 DPLL
0 (off)
0 (off)
0 (off)
0 (off)
1
2
3
5
VALSR1
and
VALSR2
registers. The
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MCR11
(IPR1