DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 74

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Auto External Frame Sync Enable (AEFSEN). This bit has two functions depending on the external frame
sync mode. See section 7.9.1.
SYNC1 Modes:
SYNC123 Mode:
Bit 6: Phase-Lock Alarm Timeout (LKATO). This bit controls how phase alarms on input clocks can be
terminated. Phase alarms are indicated by the LOCK bits in
Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local oscillator clock
signal on the REFCLK input pin. The faster edge should be selected for best jitter performance. See Section 7.3.
Bit 4: Free-Run Holdover (FRUNHO). When this bit is set to 1 the T0 DPLL holdover frequency is set to 0ppm so
the output frequency accuracy is set by the external oscillator accuracy. This effects both mini-holdover and the
holdover state.
Bit 3: External Frame-Sync Enable (EFSEN). When this bit is set to 1, the T0 DPLL looks for an external frame-
sync signal on the SYNCn pin(s). In SYNC123 mode, if AEFSEN = 1, then EFSEN is automatically cleared when
the T0 DPLL’s selected reference changes. See Section 7.9.1.
Bit 2: SONET or SDH Frequencies (SONSDH). This bit specifies the clock rate for input clocks with FREQ = 0001
in the
Section 7.4.2.
Bit 0: Revertive Mode (REVERT). This bit configures the T0 DPLL for revertive or nonrevertive operation. (The T4
DPLL is always revertive). In revertive mode, if an input clock with a higher priority than the selected reference
becomes valid, the higher priority reference immediately becomes the selected reference. In nonrevertive mode the
higher priority reference does not immediately become the selected reference but does become the highest priority
reference in the priority table (REF1 field in the
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
0 = SYNC1 Manual Mode: External frame sync is manually enabled on the SYNC1 pin when EFSEN = 1.
1 = SYNC1 Auto Mode: External frame sync is automatically enabled on the SYNC1 pin when EFSEN = 1 and
the T0 DPLL is locked to the input clock specified in FSCR3:SOURCE.
0 = EFSEN is not automatically cleared when the T0 DPLL’s selected reference changes.
1 = EFSEN is automatically cleared when the T0 DPLL’s selected reference changes.
(EFSEN must be set again by system software to enable it again.)
0 = Phase alarms on input clocks can only be cancelled by software.
1 = Phase alarms are automatically cancelled after a timeout period of 128 seconds.
0 = Rising edge
1 = Falling edge
0 = Digital holdover
1 = Free-run holdover, 0ppm
0 = Disable external frame sync; ignore SYNCn pins
1 = Enable external frame sync on SYNCn pin(s)
0 = 2048kHz
1 = 1544kHz
ICR
registers (20h to 28h). During reset the default value of this bit is latched from the SONSDH pin. See
AEFSEN
7
1
LKATO
6
1
MCR3
Master Configuration Register 3
34h
XOEDGE
5
0
PTAB1
FRUNHO
register). See Section 7.6.2.
4
0
ISR
registers.
EFSEN
3
1
SONSDH
see below
2
—
1
1
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REVERT
0
0