DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 63

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The FREQ1, FREQ2, and FREQ3 registers must be read consecutively. See Section 8.3.
Bits 7 to 0: Current DPLL Frequency (FREQ[7:0]). The full 19-bit FREQ[18:0] field spans this register, FREQ2
and FREQ3. FREQ is a two’s-complement signed integer that expresses the current frequency as an offset with
respect to the master clock frequency (see Section 7.3). When T4T0 = 0 in the
the current frequency offset of the T0 DPLL. When T4T0 = 1, FREQ indicates the current frequency offset of the T4
path. Because the value in this register field is derived from the DPLL integral path, it can be considered an
average frequency with a rate of change inversely proportional to the DPLL bandwidth. If LIMINT = 1 in the
register, the value of FREQ freezes when the DPLL reaches its minimum or maximum frequency. The frequency
offset in ppm is equal to FREQ[18:0]  0.0003068. See Section 7.7.1.6.
Application Note: Frequency measurements are relative, i.e., they measure the frequency of the selected reference
with respect to the local oscillator. As such, when a frequency difference exists, it is difficult to distinguish whether
the selected reference is off frequency or the local oscillator is off frequency. In systems with timing card
redundancy, the use of two timing cards, master and slave, can address this difficulty. Both master and slave have
separate local oscillators, and each measures the selected reference. These two measurements provide the
necessary information to distinguish which reference is off frequency, if we make the simple assumption that at
most one reference has a significant frequency deviation at any given time (i.e., a single point of failure). If both
master and slave indicate a significant frequency offset, then the selected reference must be off frequency. If the
master indicates a frequency offset but the slave does not, then the master’s local oscillator must be off frequency.
Likewise, if the slave indicates a frequency offset but the master does not, the slave’s local oscillator must be off
frequency.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Current DPLL Frequency (FREQ[15:8]). See the FREQ1 register description.
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
7
0
7
0
6
0
6
0
FREQ1
Frequency Register 1
0Ch
FREQ2
Frequency Register 2
0Dh
5
0
5
0
4
0
4
0
FREQ[15:8]
FREQ[7:0]
3
0
3
0
MCR11
2
0
2
0
register, FREQ indicates
1
0
1
0
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0
0
0
0
MCR9