DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 110

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
10.25.3 BERT Repetitive Pattern Set
These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a
pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32
bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern
was the repeating 5-bit pattern …01101… (where the rightmost bit is the one sent first and received first), then
TR.BRP1 should be loaded with ADh, TR.BRP2 with B5h, TR.BRP3 with D6h, and TR.BRP4 with 5Ah. For a
pseudorandom pattern, all four registers should be loaded with all 1s (i.e., FFh). For an alternating word pattern,
one word should be placed into TR.BRP1 and TR.BRP2 and the other word should be placed into TR.BRP3 and
TR.BRP4. For example, if the DDS stress pattern “7E” is to be described, the user would place 00h in TR.BRP1,
00h in TR.BRP2, 7Eh in TR.BRP3, and 7Eh in TR.BRP4 and the alternating word counter would be set to 50
(decimal) to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be sent and received.
10.25.4 BERT Bit Counter
The BERT Bit Counter is comprised of TR.BBC1, TR.BBC2, TR.BBC3, and TR.BBC4. Once BERT has achieved
synchronization, this 32-bit counter increments for each data bit (i.e., clock) received. Toggling the LC control bit in
TR.BC1 can clear this counter. This counter saturates when full and sets the BBCO status bit.
10.25.5 BERT Error Counter
The BERT Error Counter is comprised of TR.BEC1, TR.BEC2, and TR.BEC3. Once BERT has achieved
synchronization, this 24-bit counter increments for each data bit received in error. Toggling the LC control bit in
TR.BC1 can clear this counter. This counter saturates when full and sets the BECO status bit.
10.25.6 BERT Alternating Word-Count Rate
When the BERT is programmed in the alternating word mode, each word repeats for the count loaded into
TR.BAWC. One word should be placed into TR.BRP1 and TR.BRP2 and the other word should be placed into
TR.BRP3 and TR.BRP4.
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