DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 145

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: QRSS Enable (QRSS) When 0, the pattern generator configuration is controlled by PTS, PLF[0:4], and
PTF[0:4], and BSP[0:31]. When 1, the pattern generator configuration is forced to a QRSS pattern with a
generating polynomial of x
output bits are all zero.
Bit 5: Pattern Type Select (PTS) When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]) These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback is from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored when
programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y. The values
possible are outlined in Section 9.16.
7
0
7
0
-
-
QRSS
20
6
0
6
0
-
+ x
17
BPCLR
BERT Pattern Configuration Low Register
82h
BPCHR
BERT Pattern Configuration High Register
83h
+ 1. The output of the pattern generator is forced to one if the next fourteen
PTS
5
0
5
0
-
145 of 344
PLF4
PTF4
0
0
4
4
PTF3
PLF3
3
0
3
0
PLF2
PTF2
2
0
2
0
PLF1
PTF1
1
0
1
0
PTF0
PLF0
0
0
0
0