DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 292

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to
be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be
cleared and set again for subsequent loads.
Bit 6: Transmit Invert-Data Enable (TINV)
Bit 5: Receive Invert-Data Enable (RINV)
Bits 2 – 4: Pattern Select Bits (PS0 to PS2)
Bit 1: Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into
registers TR.BBC1/ TR.BBC2/ TR.BBC3/ TR.BBC4 and TR.BEC1/ TR.BEC2/ TR.BEC3 and clears the internal
count. This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period.
Must be cleared and set again for subsequent loads.
Bit 0: Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes
to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
PS
2
0
0
0
0
1
1
1
1
PS1
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
0 = do not invert the incoming data stream
1 = invert the incoming data stream
0
0
1
1
0
0
1
1
PS0
TC
0
1
0
1
0
1
0
1
7
0
Pseudorandom 2E7 - 1
Pseudorandom 2E11 - 1
Pseudorandom 2E15 - 1
Pseudorandom pattern QRSS. A 2
restrictions.
Repetitive pattern
Alternating word pattern
Modified 55 octet (Daly) pattern. The Daly pattern is a repeating 55 octet
pattern that is byte-aligned into the active DS0 time slots. The pattern is
defined in an ATIS (Alliance for Telecommunications Industry Solutions)
Committee T1 Technical Report Number 25 (November 1993).
Pseudorandom 2E9 – 1
TR.BC1
BERT Control Register 1
E0h
TINV
6
0
RINV
5
0
Pattern Definition
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PS2
20
0
4
- 1 pattern with 14 consecutive zero
PS1
3
0
PS0
2
0
LC
1
0
RESYNC
0
0