DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 112
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DS33R11
Manufacturer Part Number
DS33R11
Description
Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R11.pdf
(344 pages)
Specifications of DS33R11
Product
Framer
Number Of Transceivers
1
Supply Voltage (max)
1.89 V, 3.465 V
Supply Voltage (min)
1.71 V, 3.135 V
Supply Current (max)
100 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
BGA
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
10.27 Programmable Backplane Clock Synthesizer
The transceiver contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK
pin, referenced to the recovered receive clock (RCLKO). The synthesizer uses a phase-locked loop to generate
low-jitter clocks. Common applications include generation of port and backplane system clocks. The TR.CCR2
register is used to enable (TR.CCR2.0) and select (TR.CCR2.1 and TR.CCR2.2) the clock frequency of the BPCLK
pin.
10.28 Fractional T1/E1 Support
The transceiver can be programmed to output gapped clocks for selected channels in the receive and transmit
paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. The
receive and transmit paths have independent enables. Channel formats supported include 56kbps and 64kbps.
This is accomplished by assigning an alternate function to the RCHCLK and TCHCLK pins. Setting TR.CCR3.0 = 1
causes the RCHCLK pin to output a gapped clock as defined by the receive fractional T1/E1 function of the
TR.PCPR register. Setting TR.CCR3.2 = 1 causes the TCHCLK pin to output a gapped clock as defined by the
transmit fractional T1/E1 function of the TR.PCPR register. TR.CCR3.1 and TR.CCR3.3 can be used to select
between 64kbps and 56kbps operation. See Section
10.2
for details about programming the per-channel function.
In T1 mode no clock is generated at the F-bit position.
When 56kbps mode is selected, the LSB clock in the channel is omitted. Only the seven most significant bits of the
channel have clocks.
112 of 344
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