DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 219
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DS33R11
Manufacturer Part Number
DS33R11
Description
Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R11.pdf
(344 pages)
Specifications of DS33R11
Product
Framer
Number Of Transceivers
1
Supply Voltage (max)
1.89 V, 3.465 V
Supply Voltage (min)
1.71 V, 3.135 V
Supply Current (max)
100 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
BGA
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Spare Code Detected Condition (LSPARE) (T1 Only). Set when the spare code as defined in the
TR.RSCD1/2 registers is being received. See Section
9.7.
Bit 6: Loop-Down Code Detected Condition (LDN) (T1 Only). Set when the loop down code as defined in the
TR.RDNCD1/2 register is being received. See Section
9.7.
Bit 5: Loop-Up Code Detected Condition (LUP) (T1 Only). Set when the loop-up code as defined in the
TR.RUPCD1/2 register is being received. See Section
9.7.
Bit 4: Loss-of-Transmit Clock Condition (LOTC). Set when the TCLKT pin has not transitioned for one channel
time. Forces the LOTC pin high if enabled by TR.CCR1.0. This is a double interrupt bit. See Section 9.7.
Bit 3: Loss-of-Receive Clock Condition (LORC). Set when the RDCLKI pin has not transitioned for one channel
time. This is a double interrupt bit. See Section 9.7.
Bit 2: V5.2 Link Detected Condition (V52LNK) (E1 Only). Set on detection of a V5.2 link identification signal
(G.965). This is a double interrupt bit. See Section 9.7.
Bit 1: Receive Distant MF Alarm Condition (RDMA) (E1 Only). Set when bit 6 of time slot 16 in frame 0 has
been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This is a double
interrupt bit. See Section 9.7.
Bit 0: Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and
RNEGI. This is a double interrupt bit. See Section 9.7.
LSPARE
7
0
TR.SR3
Status Register 3
1Ah
LDN
6
0
LUP
5
0
219 of 344
LOTC
0
10.19
4
10.19
10.19
for details. This is a double interrupt bit. See Section
for details. This is a double interrupt bit. See Section
for details. This is a double interrupt bit. See Section
LORC
3
0
V52LNK
2
0
RDMA
1
0
RRA
0
0
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