STV2310D STMicroelectronics, STV2310D Datasheet - Page 17

• Manufacturer Part Number: STV2310D
• Description: Video ICs Digital Video Decodr
• Manufacturer: STMicroelectronics
• Type: High Quality front end videor

Specifications of STV2310D

• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV2310
4.2.2
The Output Sync Pulse (H, V and F) can be embedded in the digital output stream, according to the
ITU_R BT_656/601 format, using the EAV and SAV codes. The Output Sync Pulse can also be
delivered on dedicated external pins (33, 34, 35). These pins can be used specifically if the output
sync pulses are no longer compliant with the ITU_R BT_656/601 format, as non-interlaced pictures
or signals from a non-standard source (VCR). See
information.
Programming
The circuit can function in Automatic mode or use a programmable HPLL time constant. Automatic
mode is selected by default. In this case the STV2310 automatically adapts the time constant to the
reception conditions. In the case of unstable sources (such as VCRs) the circuit uses a special
user-programmable VCR time constant. This HPLL time constant's proportional gain is selected in
the HSYN_GP[7:0] bits in the
the HSYN_GI[7:0] bits in the
constant when the HTIMECSTSEL bit is reset in the
disabled).
To be automatically selected, the VCR time constant requires that the noise level be below the noise
threshold selected by the NOISE_THRESHOLD[2:0] bits in the
The Vsync search and initial Free-running modes are selected by the 5060MODE[1:0] bits in the
DDECCONT0
The (fluctuating) average sync bottom and blanking level values, based on the Hsync Pulse Bottom
Period and Composite Video Burst Period identification data, are necessary in turn to perform the
clamp correction on the CVBS signal in the analog domain. (See
programmed by the BLANKMODE[1:0] bits in the
The Active Input Video Period and small amplitude signals for the Active Input Video Period levels
which control the gain level of the AGC are programmed in the ACTITH[1:0] and SMHITH[1:0] bits
(respectively) in the
The CVBS saturation threshold is programmed in the SATLMTPT[1:0] and SATLMTLN[1:0] bits of
the
a number of samples per field (when, according to the algorithm, the number of samples is reached,
the gain is decreased).
Output mode can be forced to 50 Hz or 60 Hz by 5060MODE[1:0] bits in the the DDECCONT00
register.
To output a non-interlaced image, the chip must be set in direct parity mode by the DIRECTPARITY
bit in the
DDECCONT16
DDECCONT1F
register.
register in the event of a high level of chroma demodulation. It is expressed as
DDECCONT16
register.
DDECCONT27
DDECCONT26
register.
register. These bits also define the programmable time
register. The value for the integral gain is selected in
DDECCONT1
Section 4.12.2.1
DDECCONT22
DDECCONT25
register.
Figure
and
register (Automatic mode
Functional Description
9.) The clamp level is
Section
register.
for more
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