STV2310D STMicroelectronics, STV2310D Datasheet - Page 18

Video ICs Digital Video Decodr

STV2310D

Manufacturer Part Number
STV2310D
Description
Video ICs Digital Video Decodr
Manufacturer
STMicroelectronics
Type
High Quality front end videor
Datasheet

Specifications of STV2310D

Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-64
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Functional Description
18/113
4.3
4.3.1
The external HSync pulse can be synchronised to the End of Active Video (EAV) and the Start of
Active Video (SAV) pulses, or initialized according to the usual analog H/V pulse using the
HSYNC_SAV bit in the
Input Sample Rate Conversion
General Description
An Input Sample Rate Converter (ISRC) converts the acquisition pixel rate to a clock domain
virtually locked to the color subcarrier. This ISRC is controlled by a subcarrier phased-locked loop
(Chroma PLL). This enables comb filtering and chroma demodulation to be carried out on various
subcarrier frequencies using the same system clock sampling frequency.
The Input SRC uses the data provided by the front-end ADCs to process both the CVBS and C
flows (in the event of separated Y/C inputs, the CVBS flow = Y flow). The same processing is
applied to the CVBS and C data.
When the input video standard has been identified, its subcarrier frequency (f
Chroma PLL is locked. The Input SRC transforms the input data captured at the 27-MHz system
clock sampling frequency (f
Luma Low Signal Detection Threshold
Small Amplitude Signal
for Hsync Pulse Bottom Period
Hsync Pulse Bottom Period
CVBS Saturation Threshold
Luma Saturation Threshold
DDECCONT25
S
) to the subcarrier clock domain frequency (4 x f
Figure 9: AGC Flowchart
register.
807 + 8x
772 + 8x
256/244
Code
1020
30
18
0
Points/Line
Threshold
0 to 65
108
32
16
8
Threshold
Line
220
9
5
9
SC
SC
).
) is known and the
STV2310

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