DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 18

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
3.0
3.1
3.1.1
3.1.2
3.1.3
18
Functional Description Per E1 Channel
Transmitter Default Operation
Data Input Interface
The relative phase between E1 NRZ data (on DTDx pin) and clock (on DTCx pin) inputs can be
configured via microprocessor (DTDx data input may be sampled in the transmitter by the rising or
falling edge of the input clock DTCx: see global register AFH).
Frame Alignment
The framing method follows the rules set forth in CCITT/ITU recommendations G.704 and G.706.
The frame alignment circuit searches for the first frame alignment signal (“0011011” frameword,
bit 2-8 in time slot 0) within the incoming E1 data (DTDx). Once detected, the frame acquisition
counter is set to check bit 2 in the non-frame alignment signal (time slot 0) of the next frame. If bit
2 is one, a second un-errored frame alignment signal is checked one frame later. Next, the timing
generator counters are set and frame synchronization is declared. If bit 2 in the non-frame
alignment signal is not one, or the frame alignment signal is not found in the third frame, then a
new search is initiated.
If CRC-4 multiframing is configured (see paragraph below and
within 8 ms are used for immunity against false framing.
Once the E1 frame is synchronized, the framer will go out of synchronization after three
consecutive frame alignment signals containing single or multiple errors are received. In addition,
it is possible to configure the framing algorithm via register 0FH, so that the framer will also go out
of synchronization if three consecutive bit 2 of the non- frame alignment signal are not one. A 12-
bit microprocessor-accessible counter can be configured (see global register 0FH) to count either
the errored FAS, the errored NFAS, or the FAS and the NFAS with single or multiple errors.
If the CRC-4 multiframing is not configured, it is possible to strengthen the frame acquisition
algorithm to five consecutive frames (three FAS and two NFAS with no error) by programming
global register 0FH. This will minimize the probability of incorrect synchronization. In this case,
the frame desynchronization algorithm is also strengthened to four consecutive frame alignment
signals received that contain single or multiple errors, or four consecutive bit 2 of the non-frame
alignment signal not one (if so configured).
The Out Of Frame (OOF) alarm status is accessible to the microprocessor via the status registers.
CRC-4 Multiframe Alignment
CRC-4 multiframe alignment is used for immunity against false framing and also provides non-
intrusive error monitoring capabilities for the E1 payload.
When CRC-4 is selected as the E1 framing option the transmitter attempts to synchronize to a 16
frame multiframe structure illustrated in Table 1.
Figure
5), two correct multiframes
Datasheet