DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 20

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
3.1.4
3.1.5
3.1.5.1
3.1.5.2
3.1.5.3
3.1.6
20
AIS Detection
An AIS defect is detected in the DTDx input data when the incoming signal has two or less ZEROs
in each of two consecutive double frame periods (512 bits). This defect alarm is cleared when each
of two consecutive double frame periods contain three or more ZEROs or when the frame
alignment signal has been found.
The AIS defect alarm status is accessible to the microprocessor via the status registers.
CRC-4 Multiframe Monitoring
CRC-4 Block Errors Calculation
When the CRC-4 multiframe is synchronized, the CRC-4 bits are calculated internally based on a
sub-multiframe (as specified in recommendation ITU G704) and compared to the incoming CRC-4
value in the next sub-multiframe. The block errors are stored in a 10-bit counter that can be read by
the microprocessor. A maskable interrupt is provided for counter overflows.
Remote End Block Errors
Two bits per multiframe (RE1 and RE2) are allocated for the CRC-4 Remote End Block Errors
(REBE) indication. These errors are counted and stored in a 10 bit counter that can be read by the
microprocessor. A maskable interrupt is provided for counter overflows.
Remote Alarm
The Remote alarm bit (bit 3 in the NFAS) is used to tell the transmit end that the receive end has
detected a loss of signal or loss of frame. The remote alarm is filtered for three consecutive frames
before being declared a new value. Changes in its status is indicated to the microprocessor via a
maskable interrupt.
Retiming Elastic Store Operation
This block is used to eliminate the wander and the jitter in the incoming clock and data (DTC and
DTD). It may be non-transparent for the incoming data (see frame slips, below), but it keeps the
time slot alignment in the E1 frame.
The incoming data is converted to a byte parallel format and clocked into a 2 frame wide elastic
buffer. The write and read control logic of this elastic store are initialized by the frame
synchronization process. Once the frame is acquired, the Elastic Store is centered and the data is
read out of the elastic buffer and re-converted to a serial format using an external system clock
reference input (DRETCKREF).
If the incoming clock DTC and the system clock DRETCKREF are synchronous and phase-locked
(i.e., in the case of a synchronous network), the elastic buffer will never overflow or underflow.
If these two clocks, (DRETCKREF and DTC) do not have the same frequency, the elastic store will
overflow or underflow repetitively, depending on the frequency offset.
If the read system clock (DRETCKREF) frequency is higher than the write incoming clock (DTC)
frequency, then when the FIFO is close to underflowing, the read control logic will perform a slip
of one complete frame. This results in the repetition of the last received frame (“positive slip”).
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