DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 23

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

3.1.7
3.1.8
3.1.9
Datasheet
A maskable interrupt is also provided to indicate the inoperability of the elastic store. This alarm
indicates that the clock frequencies are so different that slippage is continual.
By setting a special configuration in register iEH, the transmit retiming 2 frame-wide elastic store
(512 bits) may be used to retime an un-framed 2.048 Mbit/s signal for wander elimination. In this
case, the read and write pointer of the FIFO are independent of the framing algorithm and operate
in complete free running mode, but the CRC-4, REBE and remote alarm monitoring are un-valid,
as the 2.048 Mbit/s input signal is considered un-framed.
The retiming elastic store can be bypassed by using the dejittering circuitry or configuring the data
path in pass-through mode (see register iEH).
De-jittering Circuitry
The de-jittering circuitry consists of the dejitter FIFO and a jitter attenuator or phase lock loop.
This function can be bypassed by using the retiming function or configuring the data path in pass-
through mode (see register iEH).
The dejitter FIFO is a 32-bit asynchronous FIFO, whose write clock is the input gapped clock
(DTCx) at 2.048MHz +/- 50 ppm average frequency, and whose read clock is the phase-locked and
filtered output of the jitter attenuator (the ADPLL).
The jitter attenuator is a second order All Digital Phase Lock Loop with a 2.0 Hz loop bandwidth.
The reference and sample clock of the digital PLL is provided by the high speed clock input pin
DPLLCKREF at 65.536 MHz +/- 50 ppm. DPLLCKREF reference clock is provided by an
external crystal oscillator. When the de-jittering circuitry is not selected in a transmitter, the high
speed clock is shut down in this specific transmitter to save power consumption.
A maskable interrupt is provided to indicate dejitter FIFO overflows.
AIS Signal Insertion
An AIS signal (unframed all ones signal) can be generated using the external clock input
DRETCKREF at 2.048 MHz +/- 50 ppm (if the transmitter is configured to operate in retiming or
passed through mode) or using the high-speed ADPLL reference clock at 65.536 MHz +/- 50 ppm
divided by 32 (if the transmitter is configured to operate in dejitter mode), as a blue clock on the E1
transmitter output.
When the transmitter is configured to operate in dejitter mode, an AIS signal may be automatically
hardware inserted when enabled (see registers iEH and AFH), if the dejitter ADPLL is unlocked
and the FIFO crashed. In this case, the AIS blue clock is derived from the high-speed PLL
reference clock (+/- 50 ppm), and the transition from non-AIS clock to AIS blue clock (and the
inverse) is always smooth. The AIS state is accessible to the microprocessor via the global status
register 9FH.
Line Coding HDB3
The serial E1 output is a HDB3 signal output on TPOSD and TNEGD. The output clock is TCLK
(2.048 MHz). For testing, it is possible to insert (microprocessor configurable) BPV errors on
TPOSD and TNEGD output data. A single code error, one error every 1024 bits (BER 10-3), one
error every multiframe, or one error every second may be inserted.
If the HDB3 encoder is not used, TPOSD is used as an NRZ output.
LXT6282
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