DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 32

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
4.1.3
4.1.4
4.1.5
32
Bit 2
Bit 1
Bit 0
Bit
<7:0>
Bit <7:0>
Bit <7:0>
Bit
Bit
Bit
Bit
XmtChannel
XMTINT <7:0>
AutotestCnfg
ADPLLTest
CntrTest
RcvChannel RCVINT
<7:0>
ChipID [7:0]
Name
Name
These next two registers (2FH and 3FH) indicate which channel (receiver or transmitter) has
caused an interrupt.
For example, when a channel incurs a receive LOS alarm event, if the interrupt is enabled, the
LosInt bit in the interrupt register will be set and causing the device interrupt pin to become active.
The microcontroller would then read the Receive E1 Channel interrupt register 3FH to determine
the channel in alarm. Next the Channel Interrupt Registers Receive j1H would be read to identify
the alarm. Finally, the status register j3H is read to determine the current alarm state. This last read
would also clear the corresponding interrupt register.
IND_XMTE1_CHN - Individual Transmit E1 Channel Interrupt (2FH)
IND_RCVE1_CHN - Individual Receive E1 Channel Interrupt (3FH)
CHIP_ID_NMB - Chip ID Number (4FH)
This register can only be read. It is used to identify the version of the chip.
Name
Name
This bit configures the generation of the test pattern sequence as framed
or unframed (both test pattern sequences are described in 0.151)
0 - Unframed (PBRS2E15-1 sequence).
1 - CRC-4 framed sequence. The PRBS2E15-1 sequence is transmitted
in time slot 1 to 31 (and stopped during timeslot 0.)
This bit should always be set to 0 during normal operation. It allows
faster testing of the eight digital PLLs during simulation.
0 - Normal operation
1 - Very fast tracking PLLs
This bit should always be set to 0 during normal operation. It allows
faster testing of the overflow interrupt functionality during simulation.
0 - Normal operation
1 - set overflow count: error counter 4; retiming slip counters: 2
This field contains the chip identification value
This register indicates which E1 channel transmitter has
caused an interrupt.
This register indicates which E1 channel receiver has caused
an interrupt.
Label
Label
Label
Label
Type
RO
Type
RO
Type
R/W
R/W
R/W
Type
RO
Datasheet
Default
Default
Default
Default
01H
0
1
0
0
0