DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 27

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

3.1.11.2
3.1.12
3.1.12.1
3.1.12.2
Datasheet
Both cycles require the CSB pin to be LOW and the uP to drive the A[7..0] address pins. In the
case of the write cycle, the uP is also required to drive the DATA [7..0] data pins. In the case of the
read cycle, the LXT6282 drives the DATA [7..0] data pins.
When a multiplexed data/address bus is used, the falling edge of the ALE input latches the address
provided on the muxed bus (the muxed bus will be connected to both the A[7..0] and DATA[7..0]).
If the address and data are not multiplexed the ALE pin should be tied HIGH.
Motorola Interface
The Motorola interface is indicated by driving the MCUTYPE input pin HIGH. It uses the WRB/
RWB input pin as RWB and the RDB/E input pin as E.
A read cycle is indicated to the LXT6282 by the uP forcing a HIGH on the RWB pin. A write cycle
is indicated to the LXT6282 by the uP forcing a LOW on the RWR pin.
A LOW on the E input initiates both cycles. The E input is connected to the E output from the
Motorola uP and is typically a 50% duty cycle waveform with a frequency derived from the uP
clock.
Both cycles require the CSB pin to be LOW and the uP to drive the A[7..0] address pins. In the
case of the write cycle, the uP is also required to drive the DATA [7..0] data pins. In the case of the
read cycle, the LXT6282 drives the DATA [7..0] data pins.
When a multiplexed data/address bus is used, the falling edge of the ALE input latches the address
provided on the muxed bus (the muxed bus will be connected to both the A[7..0] and DATA[7..0]).
If the address and data are not multiplexed the ALE pin should be tied HIGH.
Iinterrupt Handling
Interrupt Sources
There are three types of interrupt sources:
Interrupt Enables
In order for an interrupt source to affect the state of the INT output pin its associated interrupt
enable bit must be SET. The setting (whether it is 0 or 1) of the interrupt enables does not affect the
updating of the status registers or counters.
Assuming the interrupt enable for a particular interrupt source is SET and the interrupt source is
active, its interrupt bit will be SET. The primary difference between each interrupt type is the way
its respective interrupt bit is cleared.
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Status change of a monitoring process: For example, the LXT6282 monitors the incoming E1
frame for the correct framing pattern and updates the OofSt and LofSt status bits to indicate
presence or absence of Out Of Frame and Loss Of Frame conditions. When the value of these
status bits change an interrupt is generated if enabled.
Event Occurrence: For example, positive and negative slips as well as FIFO overflows are
considered “events” and can generate interrupts if enabled.
Counter overflows: For example, the LXT6282 monitors the E1 frame structure for framing
errors. These errors are recorded in a counter whose overflow can cause an interrupt if
enabled.
LXT6282
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