DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 40

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
4.2.11
4.3
40
Bit <7:4>
Bit <3:0>
Bit <7:6>
Bit <5:0>
Bit
Bit
Unused
RetFifoStatus<5:0>
RetNegCnt[3:0]
RetPosCnt[3:0]
XMT_RTMBUF_STAT - Transmitter Retiming Buffer Status (iDH)
(i = [0 to 7] and corresponds to the E1 channel number)
A write to the register (register iDH) causes the Retiming elastic store status bits to be buffered.
The contents of the buffer can then be read.
If WritePointerValue < ReadPointerValue then
else
Receive Side Registers
The registers described in this section are related to the E1 receivers alarm status and configuration.
There are eight E1 receivers in the chip, and 14 registers per E1 receiver. The 4 MSB bits of the
register addresses indicate the E1 channel number (4 MSB bits [from 8 to 15] minus 8 correspond
to the E1 channel number: from 0 to 7)
The eight receivers are each capable of generating nine alarm types. Any one of these alarms (if
enabled) can cause the device interrupt pin to become active.
Each E1 receiver alarm has three registers associated with it:
•
•
RetFifoStatus[5..0] = 64 + WritePointerValue - ReadPointerValue
Interrupt source: This register set will identify the alarm(s) that triggered the interrupt
Alarm status: This register contains the current status of the alarms. When this register is read,
the corresponding interrupts will be cleared
Name
RetFifoStatus[5..0] = WritePointerValue - ReadPointerValue
Name
The RetNegCnt[3..0] counter (4 MSB bits of
register iCH) counter increments each time a
negative slip is detected in the retiming elastic
buffer (one complete frame is lost).
The RetPosCnt[3..0] counter (4 LSB bits of
register iCH) increments each time a positive
slip is detected in the retiming elastic buffer
(one complete frame is repeated).
The RetFifoStatus[5..0] bits make an indication of
the content of the Retiming 2 frame-wide elastic
store. This value, coded on 6 bits, corresponds to the
difference between the read and the write pointer of
the FIFO and may be used for wander monitoring
and delay calculation.
Label
Label
Type
RO
RO
Type
RO
<0, 1, 0, 1, 0,
Default
Datasheet
Default
0
0
0>