DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 34

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
4.1.9
4.2
34
Bit 7
Bit 6
Bit 5
Bit 4
Bit
<3:0>
Bit
CnfTxClkIn
CnfTxClkOut
CnfRxClkIn
CnfRxClkOut
DjtAisSetWinNum[3:0]
GLOB_CONF - Global Operational Configuration 3 (AFH)
Transmit Side Registers
The registers described in this section are related to the E1 transmitters alarm status and
configuration.
There are eight E1 transmitters in the chip, and 14 registers per E1 transmitter. The 4 MSB bits of
the register addresses indicate the E1 channel number (from 0 to 7). The eight transmitters are each
capable of generating 12 alarm types. Any one of these alarms (if enabled) can cause the device
interrupt pin to become active.
Each E1 transmitter alarm has three registers associated with it:
Name
Clock Edges specification at the data interfaces:
This bit Configures the phase relation between clock and data at
the transmitter inputs (DTCx and DTDx input pins).
0 - DTDx input data is sampled in the chip by the falling edge of
DTCx clock.
1 - DTDx input data is sampled in the chip by the rising edge of
DTCx clock.
This bit configures the phase relation between clock and data at
the transmitters outputs (TCLKx and TPOSDx/TNEGDx output
pins).
0 - TPOSDx/TNEGDx output data are sampled by the rising edge
of TCLKx clock.
1- TPOSDx/TNEGDx output data are sampled by the falling edge
of TCLKx clock.
This bit configures the phase relation between clock and data at
the receivers inputs (RCLKx and RPOSDx/RNEGDx input pins).
0 - RPOSDx/RNEGDx input data are sampled in the chip by the
rising edge of RCLKx clock.
1 - RPOSDx/RNEGDx input data is sampled in the chip by the
falling edge of RCLKx clock.
This bit configures the phase relation between clock and data at
the receivers outputs (MTCx and MTDx output pins).
0 - MTDx output data are sampled by the falling edge of MTCx
clock.
1- MTDx output data are sampled by the rising edge of MTCx
clock.
Consecutive windows for setting AIS in the transmitters (dejitter
mode):
These bits are only relevant in dejitter mode (Transmitter) and are
common for the eight transmitters when hardware AIS is enabled
(see register iEH).
Number of consecutive 200 ms windows that must detect dejitter
ADPLL unlocked and dejitter FIFO crash to insert AIS and switch
to the blue clock on the transmitter output.
(Detection time = DjtAisSetWinNum *200 ms.)
(Note: DjtAisSetWineNum = 0 => immediate insertion of AIS after
detection of dejitter FIFO crash alarm)
Label
Type
R/W
R/W
R/W
R/W
R/W
Datasheet
Default
0
0
0
0
0