DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 41

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

4.3.1
Datasheet
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Unused
AutoTestEn
RcvBclkEn
RcvCrc-4En
RcvLosFlt
RcvAisFrc
RcvAisEn
RcvLnCodeSel
Status alarms will generate an interrupt both when the alarm changes from inactive to active or
active to inactive. The overflow alarms generate an interrupt when detected.
Updating the status register is controlled with the AlmUpdsbl bit in global register 0FH. When low,
the status registers are updated once every frame, regardless of the interrupt state. When high,
status alarm memory updates will be disabled. When accessing status alarm memory, the
microprocessor should SET AlmUpdateDsbl so that the microprocessor will have uncontested
access to this memory.
RCV_CONF- Receiver Configuration (jEH)
(j =[8 to F] and corresponds to the eight different E1 channel numbers)
This register configures a particular E1 channel receiver parameters.
Name
•
Interrupt Enable: This register contains the interrupt enables for all alarms
Enable/disable test pattern generator (the contents of the sequence
is configured in global register 1FH).
0 - Normal mode (disable autotest)
1 - Enable autotest
Enable/disable hardware switches to blue clock during Loss Of
Signal condition.
0 - Disable hardware clock switch because of LOS
1 - Enable hardware clock switch because of LOS
Enable/disable CRC-4 monitoring and multiframing in the E1
receiver (on RPOSD/RNEGD data input from the LIU).
0 - Disable. In this case, the receiver checks the errors in the
receive E1 frameword (every two frames) and counts them in the
RxErrCnt error counter. CRC multiframing is also disabled
1 - Enable. The chip performs a CRC-4 check on the incoming E1.
The blocks in error are counted in the RxErrCnt errors counter. CRC
multiframing is also enabled.
Configure LOS alarm filtering (on RLOS input signal).
0 - No filtering
1 - LOS filtering. The LOS condition must be maintained for 128
clock cycles
Force AIS generation from the receive data and clock inputs (from
the LIU) to the receiver output (to the multiplexer) via software.
0 - Disable
1 - Enable
Enable/disable hardware AIS generation from the receive data and
clock inputs (from the LIU) to the receiver output (to the PDH/SDH
multiplexer).
0 - Disable AIS generation because of LOS
1 - Enable AIS generation because of LOS
Line interface coding (on RPOSD/RNEGD receive data)
0 - HDB3
1 - NRZ
Label
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LXT6282
Default
0
0
0
0
0
0
0
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