DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 50

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
50
DATA<7:0> access time from active read
DATA<7:0> hold from inactive read
DATA<7:0> High impedance from inactive read
Valid read pulse width
Inactive read to inactive INT (due to reset on read
feature)
A<7:0> setup time to write cycle end
A<7:0> hold time from inactive write
A<7:0> setup time to latch
A<7:0> hold time from latch
Valid latch pulse width
ASB rising edge to write cycle end setup
1. For non-multiplexed Address and Data bus (
2. For multiplexed Address and Data bus (
3. T is the minimum cycle time of either DTCi, either, DRETCKREF, or MTCi (typically 488 ns for E1)
1. For non-multiplexed Address and Data bus (
2. For multiplexed Address and Data bus (
3. T is the minimum cycle time of either DTCi, either, DRETCKREF, or MTCi (typically 488 ns for E1)
A<7:0>
CSB
WRB
INT
DATA<7:0>
ASB
Table 11. Microprocessor Data Read Timing Parameters
Figure 11. Microprocessor Write Timing
Table 12. Microprocessor Data Write Timing Parameters
MicroProcessor Write Timing (Intel Mode)
(considering outputs with a 50pF load)
t
SALW
Parameter
Parameter
t
VL
t
SCW
t
SLW
t
SAW
t
t
HALW
VWR
t
SDW
ASB
AS
t
HDW
used as address latch enable)
ASB
AS
t
t
HAW
INTH
used as address latch enable)
tied high)
t
HCW
tied high)
Symbol
Symbol
t
t
t
t
HALW
SALW
t
INTH
HAW
t
SLW
t
t
t
t
t
SAW
ADR
HDR
ZDR
VRD
VL
2
A<7:0>
ASB
RWB
E
INT
DATA<7:0>
2
3
CSB
1
2
2
T + 6
MicroProcessor Write Timing (Motorola Mode)
Min
Min
20
4
6
2
4
2
5
7
t
SALW
t
VL
t
SCW
Typ
Typ
t
SRWB
t
SAW
t
SLW
t
t
VWR
2*T + 21
HALW
Max
Max
t
15
13
SDW
t
t
HRWB
HDW
t
t
HAW
INTH
Datasheet
t
HCW
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns