ISP1508BET STEricsson, ISP1508BET Datasheet - Page 20

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1508A_ISP1508B_2
Product data sheet
Fig 7.
CHIP_SEL
DATA[7:0]
CLOCK
STP
NXT
DIR
Interface behavior with respect to the CHIP_SEL pin
8.11.2 Interface behavior with respect to the CHIP_SEL pin
Hi-Z (input)
Hi-Z (input)
The interface protect feature prevents unwanted activity of the ISP1508 whenever the
ULPI interface is not correctly driven by the link. For example, when the link powers up
more slowly than the ISP1508.
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.
The use of the CHIP_SEL pin is optional. When not active, ULPI pins will be 3-stated and
the internal circuitry is powered down. If the CHIP_SEL pin is not used, it must be
connected to V
ULPI interface behavior when the CHIP_SEL pin is asserted and subsequently
de-asserted.
CC(I/O)
in the ISP1508A and to GND in the ISP1508B.
Rev. 02 — 13 March 2008
Hi-Z (ignored)
Hi-Z
Hi-Z (ignored)
ISP1508A; ISP1508B
Hi-Z
t
PWRDN
Hi-Z (ignored)
ULPI HS USB OTG transceiver
Figure 7
© NXP B.V. 2008. All rights reserved.
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