ISP1508BET STEricsson, ISP1508BET Datasheet - Page 83

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Signal mapping during low-power mode . . . . .22
Table 11. Signal mapping for 6-pin serial mode . . . . . . .23
Table 12. Signal mapping for 3-pin serial mode . . . . . . .23
Table 13. UART signal mapping . . . . . . . . . . . . . . . . . . .24
Table 14. Operating states and their corresponding resistor
Table 15. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .29
Table 16. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .30
Table 17. LINESTATE[1:0] encoding for upstream facing
Table 18. LINESTATE[1:0] encoding for downstream facing
Table 19. Encoded V
Table 20. V
Table 21. Encoded USB event signals . . . . . . . . . . . . . .33
Table 22. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .37
Table 23. Link decision times . . . . . . . . . . . . . . . . . . . . .38
Table 24. Register map . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 25. Vendor ID Low register (address R = 00h) bit
Table 26. Vendor ID High register (address R = 01h) bit
Table 27. Product ID Low register (address R = 02h) bit
Table 28. Product ID High register (address R = 03h) bit
Table 29. Function Control register (address
Table 30. Function Control register (address
Table 31. Interface Control register (address
ISP1508A_ISP1508B_2
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
OTG Control register power control bits . . . . . .8
Recommended V
Allowed crystal or clock frequency on the XTAL1
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
External capacitor values for 13 MHz or 19.2 MHz
clock frequency . . . . . . . . . . . . . . . . . . . . . . . .11
External capacitor values for 24 MHz or 26 MHz
clock frequency . . . . . . . . . . . . . . . . . . . . . . . .11
Pin states in power-down mode . . . . . . . . . . . .20
ULPI signal description . . . . . . . . . . . . . . . . . .21
settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ports: peripheral . . . . . . . . . . . . . . . . . . . . . . . .31
ports: host . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
applications . . . . . . . . . . . . . . . . . . . . . . . . . . .32
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
BUS
indicators in RXCMD required for typical
BUS
voltage state . . . . . . . . . . . . . .31
BUS
capacitor value . . . . . . . .9
Rev. 02 — 13 March 2008
Table 32. Interface Control register (address R = 07h to 09h,
Table 33. OTG Control register (address R = 0Ah to 0Ch,
Table 34. OTG Control register (address R = 0Ah to 0Ch,
Table 35. USB Interrupt Enable Rising register (address
Table 36. USB Interrupt Enable Rising register (address
Table 37. USB Interrupt Enable Falling register (address
Table 38. USB Interrupt Enable Falling register (address
Table 39. USB Interrupt Status register (address R = 13h)
Table 40. USB Interrupt Status register (address R = 13h)
Table 41. USB Interrupt Latch register (address R = 14h) bit
Table 42. USB Interrupt Latch register (address R = 14h) bit
Table 43. Debug register (address R = 15h) bit
Table 44. Debug register (address R = 15h) bit
Table 45. Scratch register (address R = 16h to 18h,
Table 46. Carkit Control register (address R = 19h to 1Bh,
Table 47. Carkit Control register (address R = 19h to 1Bh,
Table 48. Power Control register (address R = 3Dh to 3Fh,
Table 49. Power Control register (address R = 3Dh to 3Fh,
Table 50. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 51. Recommended operating conditions . . . . . . . . 59
Table 52. Static characteristics: supply pins . . . . . . . . . . 60
Table 53. Static characteristics: digital pins . . . . . . . . . . 60
Table 54. Static characteristics: digital pin FAULT . . . . . 61
Table 55. Static characteristics: digital pin PSW_N . . . . 61
Table 56. Static characteristics: analog pins (DP, DM) . . 61
Table 57. Static characteristics: analog pin V
W = 07h, S = 08h, C = 09h) bit description . . . 53
W = 0Ah, S = 0Bh, C = 0Ch) bit allocation . . . 54
W = 0Ah, S = 0Bh, C = 0Ch) bit description . . 54
R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 56
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 56
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
W = 16h, S = 17h, C = 18h) bit description . . . 57
W = 19h, S = 1Ah, C = 1Bh) bit allocation . . . . 58
W = 19h, S = 1Ah, C = 1Bh) bit description . . 58
W = 3Dh, S = 3Eh, C = 3Fh) bit allocation . . . 58
W = 3Dh, S = 3Eh, C = 3Fh) bit description . . 58
ISP1508A; ISP1508B
ULPI HS USB OTG transceiver
© NXP B.V. 2008. All rights reserved.
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BUS
. . . . . . 63
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