ISP1508BET STEricsson, ISP1508BET Datasheet - Page 27

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1508A_ISP1508B_2
Product data sheet
Fig 8.
Fig 9.
CLOCK
CLOCK
DATA[7:0]
DATA[7:0]
UART
CLOCK
mode
CLOCK
(1) Clock remains powered when the CLOCK_SUSPENDM register bit is logic 1.
(2) Clock is powered down when the CLOCK_SUSPENDM register bit is logic 0 (default).
(1) Clock remains powered when the CLOCK_SUSPENDM register bit is logic 1.
(2) Clock is powered down when the CLOCK_SUSPENDM register bit is logic 0 (default).
NXT
STP
DIR
(1)
(2)
UART
mode
Interface behavior when entering UART mode
Interface behavior when exiting UART mode
NXT
STP
(2)
DIR
(1)
TXCMD
(REGW)
UART mode signals
Rev. 02 — 13 March 2008
DATA
0000 0000
ISP1508A; ISP1508B
0001 0001
ULPI HS USB OTG transceiver
turnaround
turnaround
UART mode signals
© NXP B.V. 2008. All rights reserved.
synchronous
mode signals
004aaa867
004aaa865
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