ISP1508BET STEricsson, ISP1508BET Datasheet - Page 39

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 23.
ISP1508A_ISP1508B_2
Product data sheet
Packet sequence High-speed
Transmit-Transmit
(host only)
Receive-Transmit
(host or
peripheral)
Receive-Receive
(peripheral only)
Transmit-Receive
(host or
peripheral)
Fig 15. High-speed transmit-to-transmit packet timing
CLOCK
DATA
DP or
DIR
[7:0]
STP
NXT
DM
D
N 1
Link decision times
D
N
link delay
15 to 24
1 to 14
1
92
DATA
TX end delay (two to five clocks)
Full-speed
link delay
7 to 18
7 to 18
1
80
EOP
Low-speed
link delay
77 to 247
77 to 247
1
718
Rev. 02 — 13 March 2008
link decision time (15 to 24 clocks)
USB interpacket delay (88 to 192 high-speed bit times)
Definition
Number of clocks a host link must wait before driving the
TXCMD for the second packet.
In high-speed, the link starts counting from the assertion of
STP for the first packet.
In full-speed, the link starts counting from the RXCMD,
indicating LINESTATE has changed from SE0 to J for the first
packet. The timing given ensures inter-packet delays of 2 bit
times to 6.5 bit times.
Number of clocks the link must wait before driving the TXCMD
for the transmit packet.
In high-speed, the link starts counting from the end of the
receive packet; de-assertion of DIR or an RXCMD, indicating
RxActive is LOW.
In full-speed or low-speed, the link starts counting from the
RXCMD, indicating LINESTATE has changed from SE0 to J
for the receive packet. The timing given ensures inter-packet
delays of 2 bit times to 6.5 bit times.
Minimum number of clocks between consecutive receive
packets. The link must be capable of receiving both packets.
Host or peripheral transmits a packet and will time-out after
this amount of clock cycles if a response is not received. Any
subsequent transmission can occur after this time.
ISP1508A; ISP1508B
IDLE
ULPI HS USB OTG transceiver
(one to two clocks)
© NXP B.V. 2008. All rights reserved.
TXCMD
TX start delay
004aaa712
SYNC
D0
38 of 86
D1