ISP1508BET STEricsson, ISP1508BET Datasheet - Page 40

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1508A_ISP1508B_2
Product data sheet
Fig 16. High-speed receive-to-transmit packet timing
CLOCK
DP or
DATA
[7:0]
STP
NXT
DIR
DM
D
N 4
DATA
10.6 Preamble
D
N 3
D
EOP
N 2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the
ISP1508 operates just as in full-speed mode, and sends all data with the full-speed rise
time and fall time. Whenever the link transmits a USB packet in preamble mode, the
ISP1508 will automatically send a preamble header at full-speed bit rate before sending
the link packet at low-speed bit rate. The ISP1508 will ensure a minimum gap of four
full-speed bit times between the last bit of the full-speed PRE PID and the first bit of the
low-speed packet SYNC. The ISP1508 will drive a J for at least one full-speed bit time
after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus.
An example transmit packet is shown in
In preamble mode, the ISP1508 can also receive low-speed packets from the full-speed
bus.
(three to eight clocks)
D
RX end delay
N 1
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
Rev. 02 — 13 March 2008
link decision time (1 to 14 clocks)
IDLE
Figure
ISP1508A; ISP1508B
17.
ULPI HS USB OTG transceiver
(one to two clocks)
TXCMD
TX start delay
© NXP B.V. 2008. All rights reserved.
SYNC
D0
004aaa713
39 of 86
D1