ISP1761BEGE STEricsson, ISP1761BEGE Datasheet
ISP1761BEGE
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ISP1761BEGE Summary of contents
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ISP1761 Hi-Speed USB On-The-Go controller Rev. 09 — 15 April 2010 1. General description The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with advanced ST-Ericsson slave host controller and the ST-Ericsson ISP1582 peripheral controller. ...
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Separate IRQ, DREQ and DACK lines for the host controller and the peripheral controller Integrated multi-configuration FIFO Double-buffering scheme increases throughput and facilitates real-time data transfer Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI Tolerant I/O ...
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Slave DMA, fully autonomous and supports multiple configurations Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT endpoint Integrated 8 kB memory Software-controllable connection to the USB bus, SoftConnect 3. Applications The ISP1761 can be used ...
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... Ordering information Commercial Package description product code LQFP128; 128 leads; body 14 × 20 × 1.4 (mm) ISP1761BEUM LQFP128; 128 leads; body 14 × 20 × 1.4 (mm) ISP1761BEGE TFBGA128; 128 balls; body 9 × 9 × 0.8 (mm) ISP1761ETUM CD00222703 Product data sheet Packing 13 inch tape and reel dry pack ...
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... This figure shows the LQFP pinout. For the TFBGA ballout, see All ground pins should normally be connected to a common ground plane. Fig 1. Block diagram CD00222703 Product data sheet V CC(I/O) 10, 40, 48, 59, 67, 75, 83, 94, 104, 115 ISP1761BEUM ISP1761BEGE SEL16/32 HC PTD MEMORY (3 kB) HC PAYLOAD DC BUFFER MEMORY MEMORY MEMORY (60 kB) ...
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... Pinning information 6.1 Pinning Fig 2. Pin configuration (LQFP128); top view Fig 3. Pin configuration (TFBGA128); top view CD00222703 Product data sheet 1 102 ISP1761BEUM ISP1761BEGE 38 65 004aaa506 ball A1 index area ISP1761ETUM Rev. 09 — 15 April 2010 ISP1761 Hi-Speed USB OTG controller 004aaa551 © ST-ERICSSON 2010. All rights reserved. ...
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Pin description Table 2. Pin description [1][2] Symbol Pin LQFP128 TFBGA128 OC3_N 1 C2 REF5V GNDA 4 A1 REG1V8 CC(5V0 CC(5V0) GND(OSC REG3V3 9 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 PSW2_N 28 M1 GND(RREF3 RREF3 30 N1 [6] GNDA 31 P2 DM3 32 P1 GNDA 33 R2 DP3 34 R1 PSW3_N 35 T1 GNDD 36 T2 DATA0 37 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA9 49 T8 REG1V8 50 R8 DATA10 51 P9 DATA11 52 T9 GNDC 53 R9 DATA12 54 T10 GNDD 55 R10 DATA13 56 P11 DATA14 57 T11 DATA15 58 R11 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA21 66 R15 V 67 P15 CC(I/O) DATA22 68 T16 DATA23 69 R16 DATA24 70 P16 GNDD 71 N16 DATA25 72 N15 DATA26 73 M15 DATA27 74 M16 V 75 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 A2 84 H15 REG1V8 85 G16 A3 86 H14 A4 87 F16 GNDC 88 G15 A5 89 F15 GNDD 90 E16 A6 91 F14 A7 92 E15 A8 93 D16 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 CS_N 106 A12 RD_N 107 B12 WR_N 108 B11 GNDD 109 A11 BAT_ON_N 110 C10 DC_IRQ 111 A10 HC_IRQ 112 B10 DC_DREQ 113 A9 HC_DREQ 114 B9 V 115 C8 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 RESET_N 122 B6 GNDA 123 B5 C_B 124 A5 C_A 125 B4 V 126 A4 CC(C_IN) OC1_N/V 127 B3 BUS OC2_N 128 A3 [1] Symbol names ending with underscore N, ...
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Functional description 7.1 ISP1761 internal architecture: advanced ST-Ericsson slave host controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the advanced ST-Ericsson slave host controller. The EHCI is the latest generation ...
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Fig 4. Internal hub 7.1.1 Internal clock scheme and port selection Figure 5 shows the internal clock scheme of the ISP1761. The ISP1761 has three ports. Fig 5. ISP1761 clock scheme CD00222703 Product data sheet EHCI ROOT HUB PORTSC1 ENUMERATION ...
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Port 2 does not need to be enabled using software if only port 1 or port 3 is used. No port needs to be disabled by external pull-up resistors, if not used. The DP and DM of the unused ports ...
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The total amount of memory allocated to the payload determines the maximum transfer size specified by a PTD, a larger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context switching, resulting ...
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The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously fill up another block area in the RAM. A PTD and its payload can ...
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USB HIGH-SPEED USB BUS HOST AND TRANSACTION TRANSLATOR (FULL-SPEED AND LOW-SPEED) address data (64 bits) Fig 6. Memory segmentation and access block diagram Both the CPU interface logic and the USB host controller require access to the internal ...
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In the case of a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the number of bursts that will complete a certain transfer length. In PIO ...
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PIO mode access, register read cycle The PIO register read access is similar to a general register access not necessary to set a pre-fetching address before a register read. The ISP1761 register read address will not automatically ...
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It is also possible that the system’s DMA will perform a memory-to-memory type of transfer between the system memory and the ISP1761 memory. The ISP1761 will be accessed in PIO mode. Consequently, memory read operations must be preceded by initializing ...
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Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match IRQ settings of the host processor. By default, interrupt is level-triggered and active LOW. 4. ...
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With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer (ISO, INT and bulk), software can determine which PTDs get priority and an interrupt will be generated when the AND or OR ...
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The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz. No external components are required for the PLL operation. 7.6 Power management The ISP1761 implements a flexible ...
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ISP1761 will switch back to suspend mode after the specified time. The maximum delay that can be programmed in the clock-off count field is approximately 500 ms. Additionally, the Power Down Control register allows ISP1761 internal blocks to ...
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... CD00222703 Product data sheet V CC(5V0 10, 40, 48, V CC(I/O) 59, 67, 75, 83, 94, 104, 115 REG1V8 85 10 µF ISP1761BEUM ISP1761BEGE REG1V8 5, 50, 118 100 nF REG3V3 9 10 µF 100 nF V 3.3 V CC(C_IN) 126 100 nF Rev. 09 — 15 April 2010 ISP1761 Hi-Speed USB OTG controller 3 ...
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... GPIO pins of the processor. This helps to reduce the suspend current off during suspend reset pulse is required when power is switched CC(5V0) back on, before the resume programming sequence starts. CD00222703 Product data sheet ISP1761BEUM ISP1761BEGE 6, 7, 10, 40 CC(5V0) CC(I/O) 48, 59, 67, 75, 83, 94, 104, 115, 126 ...
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... CD00222703 Product data sheet controlled by the CPU V CC(5V0 10, 40, 48, V CC(I/O) 59, 67, 75, 83, 94, 104, 115 REG1V8 85 ISP1761BEUM ISP1761BEGE REG1V8 5, 50, 118 REG3V3 9 10 µF V CC(C_IN) 126 Pin status during hybrid mode Rev. 09 — 15 April 2010 ISP1761 Hi-Speed USB OTG controller 3 100 nF 1 ...
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For an overcurrent limit of 500 mA per port, a PMOS transistor with R approximately 100 mΩ is required PMOS transistor with a lower R analog overcurrent detection can be adjusted using a series resistor; see ΔV = ...
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To give a better view of the functionality, dips and t4 to t5. If the dip too short, that is, < 11 μs, the internal POR pulse will not react and ...
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Host controller Table 8 shows the bit description of the registers. • All registers range from 0000h to 03FFh. These registers can be read or written as double word, that is 32-bit data. • Operational registers range from 0000h ...
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Table 8. Address 033Ch 0014h 0018h 0340h 0344h 0354h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register The bit description of the Capability Length (CAPLENGTH) register is given in Table 9. ...
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Bit 23 22 Symbol Reset 0 0 Access R R Bit 15 14 Symbol N_CC[3:0] Reset 0 0 Access R R Bit 7 6 Symbol PRR Reset 0 0 Access R R Table 12. Bit ...
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Bit 23 22 Symbol Reset 0 0 Access R R Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 6 Symbol Reset 1 0 Access R R Table 14. Bit Symbol ...
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Table 15. USBCMD - USB Command register (address 0020h) bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W ...
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Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol reserved Reset 0 0 Access R/W R/W [1] The reserved bits should always be written with ...
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Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 [1] Symbol reserved Reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Access R/W R/W [1] The reserved bits should always be written ...
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Table 22. Bit Symbol Description [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.2.6 PORTSC1 register The Port Status and Control (PORTSC) register (bit allocation: well reset ...
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Table 24. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. ...
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Table 26. ISO PTD Skip Map register (address 0134h) bit description Bit Symbol Access ISO_PTD_SKIP_ R/W MAP[31:0] When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its ...
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INT PTD Last PTD register The bit description of the register is given in Table 30. INT PTD Last PTD register (address 0148h) bit description Bit Symbol Access INT_PTD_LAST_ R/W PTD[31:0] Once the LastPTD bit corresponding ...
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Table 33. ATL PTD Last PTD register (address 0158h) bit description Bit Symbol Access ATL_PTD_LAST_ R/W PTD[31:0] Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking V = ...
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Table 35. Bit Symbol 31 ALL_ATX_RESET ANA_DIGI_OC DEV_DMA 10 COMN_INT 9 COMN_DMA 8 DATA_BUS_WIDTH Data Bus Width DACK_POL 5 DREQ_POL INTR_POL 1 ...
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HcChipID register Read this register to get the ID of the ISP1761. This upper word of the register contains the hardware version number and the lower word contains the chip ID. bit description of the register. Table 36. HcChipID ...
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Table 39. Bit 8.3.5 HcDMAConfiguration register The bit allocation of the HcDMAConfiguration register is given in Table 40. HcDMAConfiguration - Host Controller Direct Memory Access Configuration register (address 0330h) bit allocation Bit 31 30 Symbol ...
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Table 41. Bit Symbol DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read BURST_LEN[1:0] 1 ENABLE_DMA 0 DMA_READ_WRITE_ SEL 8.3.6 HcBufferStatus register The HcBufferStatus register is used ...
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Bit 7 6 Symbol Reset 0 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 43. Bit Symbol ISO_BUF_FILL ISO Buffer Filled: 1 INT_BUF_FILL 0 ATL_BUF_FILL ATL ...
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Table 45. Memory register (address 033Ch) bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 ...
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Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 6 Symbol Reset 0 0 Access R R [1] The reserved bits should always be written with the reset value. Table 48. Bit Symbol ...
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Table 50. Bit Symbol PORT3_EN[1: PORT2_EN[1: PORT1_EN[1:0] 8.3.11 Edge Interrupt Count register Table 51 shows the bit allocation of the register. Table 51. Edge Interrupt Count register ...
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Table 52. Bit 8.3.12 DMA Start Address register This register defines the start address select for the DMA read and write operations. See Table 53 for bit allocation. Table 53. DMA ...
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Table 55. Power Down Control register (address 0354h) bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 1 1 Access R/W R/W Bit 15 14 Symbol reserved Reset 0 0 Access R/W ...
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Table 56. [1] Bit For a 32-bit operation, the default wake-up counter value is 10 μs. For a 16-bit operation, the wake-up [1] counter value is 50 ms. In the ...
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These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN in the HW Mode Control register. register. Table 57. HcInterrupt - Host Controller Interrupt register (address 0310h) bit allocation Bit 31 30 Symbol Reset 0 0 ...
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Table 58. Bit Symbol 8 ATL_IRQ 7 INT_IRQ 6 CLKREADY 5 HCSUSP DMAEOTINT SOFITLINT 0 - 8.4.2 HcInterruptEnable register This register allows enabling or disabling of the IRQ generation because of various events as ...
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Table 59. HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 ...
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Table 60. Bit Symbol 7 INT_IRQ_E 6 CLKREADY_E 5 HCSUSP_E DMAEOTINT_E DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA SOFITLINT_E 0 - 8.4.3 ISO IRQ MASK OR register Each bit of ...
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Table 62. INT IRQ Mask OR register (address 031Ch) bit description Bit Symbol Access Value INT_IRQ_MASK_ R/W OR[31:0] 8.4.5 ATL IRQ MASK OR register Each bit of this register corresponds to one of the 32 ATL PTDs ...
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Table 66. ATL IRQ MASK AND register (address 032Ch) bit description Bit Symbol Access ATL_IRQ_ R/W MASK_AND [31:0] 8.5 Proprietary Transfer Descriptor (PTD) The standard EHCI data structures as described in Interface Specification for Universal Serial Bus ...
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High-speed bulk IN and OUT Table 67 shows the bit allocation of the high-speed bulk IN and OUT, asynchronous Transfer Descriptor. Table 67. High-speed bulk IN and OUT: bit allocation Bit ...
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Table 68. High-speed bulk IN and OUT: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - DW3 ...
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Table 68. High-speed bulk IN and OUT: bit description Bit Symbol Access NakCnt[3:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred SW — writes [14:0] 0000 ...
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Table 68. High-speed bulk IN and OUT: bit description Bit Symbol Access MaxPacket SW — writes - Length[10: NrBytesTo SW — writes - Transfer[14: reserved - — sets ...
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High-speed isochronous IN and OUT Table 69 shows the bit allocation of the high-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD). Table 69. High-speed isochronous IN and OUT: bit allocation ...
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Table 70. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW7 ISOIN_7[11:0] HW — writes ISOIN_6[11:0] HW — writes ISOIN_5[11:4] HW — writes DW6 ISOIN_5[3:0] HW ...
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Table 70. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW3 — sets — writes — writes reserved - NrBytes HW — writes ...
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Table 70. High-speed isochronous IN and OUT: bit description Bit Symbol Access MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — resets SW — ...
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High-speed interrupt IN and OUT Table 71 shows the bit allocation of the high-speed interrupt IN and OUT, periodic Transfer Descriptor (pTD). Table 71. High-speed interrupt IN and OUT: bit allocation ...
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Table 72. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW7 INT_IN_7[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[11:4] HW — writes DW6 INT_IN_5[3:0] HW ...
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Table 72. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW3 — writes SW — writes — writes reserved - — writes SW — writes 56 ...
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Table 72. High-speed interrupt IN and OUT: bit description Bit Symbol Access Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - ...
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Start and complete split for bulk Table 74 shows the bit allocation of Start Split (SS) and Complete Split (CS) for bulk, asynchronous Start Split and Complete Split (SS/CS) Transfer Descriptor. ...
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Table 75. Start and complete split for bulk: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - DW3 63 A ...
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Table 75. Start and complete split for bulk: bit description Bit Symbol Access RL[3:0] SW — writes 24 reserved - DataStartAddress SW — writes [15: reserved - DW1 ...
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Table 75. Start and complete split for bulk: bit description Bit Symbol Access NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets Table 76. Bulk I/O I/O CD00222703 ...
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Start and complete split for isochronous Table 77 shows the bit allocation for start and complete split for isochronous, split isochronous Transfer Descriptor (siTD). Table 77. Start and complete split for ...
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Table 78. Start and complete split for isochronous: bit description Bit Symbol Access DW7 reserved - ISO_IN_7[7:0] HW — writes DW6 ISO_IN_6[7:0] HW — writes ISO_IN_5[7:0] HW — ...
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Table 78. Start and complete split for isochronous: bit description Bit Symbol Access DW3 — sets HW — resets — writes — writes — writes ...
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Table 78. Start and complete split for isochronous: bit description Bit Symbol Access 31 EndPt[0] SW — writes reserved - TT_MPS_Len SW — writes [10: NrBytesTo SW — writes Transfer[14:0] 2 ...
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Start and complete split for interrupt Table 79 shows the bit allocation of start and complete split for interrupt. Table 79. Start and complete split for interrupt: bit allocation Bit 63 ...
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Table 80. Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] HW — ...
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Table 80. Start and complete split for interrupt: bit description Bit Symbol Access DW3 — sets HW — resets — writes — writes — writes ...
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Table 80. Start and complete split for interrupt: bit description Bit Symbol Access Token[1:0] SW — writes DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — ...
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OTG controller 9.1 Introduction OTG is a supplement to the Hi-Speed USB specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals primarily targeted at portable devices ...
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A-device assumes the role of a host. The A-device detects that the B-device can support HNP by getting the OTG descriptor from the B-device. The A-device will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and ...
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Host Negotiation Protocol (HNP) HNP is used to transfer control of the host role between the default host (A-device) and the default peripheral (B-device) during a session. When the A-device is ready to give up its role as a ...
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The A-device detects lack of bus activity for more than 3 ms and turns off its DP pull-up. Alternatively, if the A-device has no further need to communicate with the B-device, the A-device may turn off V 7. The ...
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START id | a_bus_req | (a_sess_vld/ & b_conn/) a_wait_vfall drv_vbus/ loc_conn/ loc_sof a_bus_drop a_peripheral drv_vbus loc_conn loc_sof/ b_conn/ & a_set_b_hnp_en id | a_bus_drop | a_aidl_bdis_tmout a_suspend drv_vbus loc_conn/ loc_sof/ Fig 14. Dual-role A-device state diagram CD00222703 Product data ...
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START id/ | b_sess_vld/ b_host chrg_vbus/ loc_conn/ loc_sof a_conn b_wait_acon chrg_vbus/ loc_conn/ loc_sof/ Fig 15. Dual-role B-device state diagram 9.4.3 HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality ...
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Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt Enable Fall registers. 3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10). 4. Set bit GLOBAL_INTR_EN of the HW Mode Control register (bit 0). When ...
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Table 84. Address OTG Timer register 0388h 038Ch Table 85. Address Device ID registers 0370h 0372h OTG Control register 0374h 0376h OTG Interrupt registers 0378h 037Ah 037Ch 037Eh 0380h 0382h 0384h 0386h OTG Timer register 0388h 038Ah 038Ch 038Eh 9.5.1 ...
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OTG Control register 9.5.2.1 OTG Control register Table 88 shows the bit allocation of the register. Table 88. OTG Control register (address set: 0374h, clear: 0376h) bit allocation Bit 15 14 Symbol Reset 0 0 Access R/S/C R/S/C Bit ...
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Table 89. [1] Bit Symbol 2 DM_PULLDOWN DM pull-down: 1 DP_PULLDOWN 0 DP_PULLUP [1] To use port host controller, write 0080 0018h to this register after power-on. To use port peripheral controller, write 0006 ...
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Table 91. Bit 9.5.3.2 OTG Interrupt Latch register The OTG Interrupt Latch register indicates the source that generated the interrupt. The status of this register bits depends on the settings of ...
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OTG Interrupt Enable Fall register Table 94 shows the bit allocation of this register that enables interrupts on transition from HIGH-to-LOW. Table 94. OTG Interrupt Enable Fall register (address set: 0380h, clear: 0382h) bit allocation Bit 15 14 Symbol ...
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Bit 7 6 Symbol B_SESS_ BDIS_ END ACON Reset 0 0 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. Table 97. Bit ...
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Bit 7 6 Symbol Reset 0 0 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. Table 99. Bit CD00222703 Product data sheet 5 4 TIMER_INIT_VALUE[7:0] 0 ...
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Peripheral controller 10.1 Introduction The design of the peripheral controller in the ISP1761 is compatible with the ST-Ericsson’ ISP1582 Hi-Speed Universal Serial Bus peripheral controller IC. The functionality of the peripheral controller in the ISP1761 is similar to the ...
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If DMA is not required by the application, DMACLKON can be permanently disabled to save current. The burst counter, DMA bus width, and the polarity of DC_DREQ and DC_DACK must accordingly be set. The ISP1761 supports only counter ...
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If bit INT_EOT in the DMA Interrupt Reason register is set, it indicates that a short or empty packet is received. This means that DMA transfer terminated. Normally, for an OUT transfer, it means that remote host wishes to terminate ...
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Table 100. Endpoint access and programmability Endpoint identifier EP6TX EP7RX EP7TX 10.3 Differences between the ISP1761 and ISP1582 peripheral controllers This section explains the variations between the ISP1761 and ISP1582 peripheral controllers in terms of register bits and their associated ...
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Peripheral controller-specific registers Table 101. Peripheral controller-specific register overview Address Register Initialization registers 0200h 020Ch 0210h 0212h 0214h 0300h 0374h Data flow registers 022Ch 0228h 0220h 021Ch 021Eh 0204h 0208h DMA registers 0230h 0234h 0238h 023Ch 0250h 0254h 0258h ...
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In response to standard USB request SET_ADDRESS, firmware must write the (enabled) peripheral address to the Address register, followed by sending an empty packet to the host. The new peripheral address is activated when the peripheral receives acknowledgment from the ...
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Table 105. Mode register (address 020Ch) bit description Bit 10.4.3 Interrupt Configuration register This 1 byte register determines the behavior and polarity of the INT output. ...
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The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you to individually configure when the ISP1761 sends an interrupt to the external microprocessor. Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or ...
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Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 110. Debug register (address 0212h) bit allocation Bit 10.4.5 ...
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Bit 15 14 Symbol IEP2TX IEP2RX Reset 0 0 Bus reset 0 0 Access R/W R/W Bit 7 6 Symbol IEVBUS IEDMA Reset 0 0 Bus reset 0 0 Access R/W R/W [1] The reserved bits should always be written ...
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Data flow registers 10.5.1 Endpoint Index register The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 byte, and the bit allocation is shown in Table 113. The following registers ...
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Table 115. Addressing of endpoint buffers Buffer name SETUP Control OUT Control IN Data OUT Data IN 10.5.2 Control Function register The Control Function register performs the buffer management on endpoints. It consists of 1 byte, and the bit configuration ...
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Table 117. Control Function register (address 0228h) bit description Bit Symbol 2 DSEN 1 STATUS 0 STALL 10.5.3 Data Port register This register provides direct access for a microcontroller to the FIFO of the indexed endpoint. Peripheral to host (IN ...
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Table 118. Data Port register (address 0220h) bit description Bit Symbol Access Value DATAPORT R/W 0000 0000h [31:0] The Data Port register description when the ISP1761 is in 16-bit mode is given in Table 119. Table 119. ...
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DcBufferStatus register This register is accessed using an index. The endpoint index must first be set before accessing this register for the corresponding endpoint. It reflects the status of the endpoint FIFO. Table 121 Remark: This register is not ...
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Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 124. Endpoint MaxPacketSize register (address 0204h) bit description Bit ...
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Table 126. Endpoint Type register (address 0208h) bit description Bit Symbol NOEMPKT 3 ENABLE 2 DBLBUF ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type as follows. 10.6 DMA registers The Generic ...
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There are two interrupts that are programmable to differentiate the method of DMA termination: the INT_EOT and DMA_XFER_OK bits in the DMA Interrupt Reason register. For details, see Table 127. Control bits for GDMA read or write (opcode = 00h/01h) ...
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Table 130. DMA commands Code 0Fh 10h 11h 12h 13h 14h to FFh - 10.6.2 DMA Transfer Counter register This 4 bytes register sets up the total byte count for a DMA transfer (DMACR). It indicates the remaining number of ...
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Bit 15 14 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W Table 132. DMA Transfer Counter register (address 0234h) bit description Bit 31 ...
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Table 134. DcDMAConfiguration - Device Controller Direct Memory Access Configuration Bit 10.6.4 DMA Hardware register The DMA Hardware register consists of 1 byte. The bit allocation is shown in This register determines the polarity of ...
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Table 137. DMA Interrupt Reason register (address 0250h) bit allocation Bit 15 14 Symbol reserved Reset 0 0 Bus reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W [1] ...
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Table 140. DMA Interrupt Enable register (address 0254h) bit allocation Bit 15 14 Symbol reserved Reset 0 0 Bus reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W [1] ...
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Table 143. DMA Burst Counter register (address 0264h) bit allocation Bit 15 14 Symbol reserved Reset 0 0 Bus reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W [1] ...
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Table 145. DcInterrupt - Device Controller Interrupt register (address 0218h) bit allocation Bit 31 30 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W Bit 23 22 Symbol EP6TX EP6RX Reset 0 0 Bus reset 0 0 Access ...
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Table 146. DcInterrupt - Device Controller Interrupt register (address 0218h) bit Bit 10.7.2 DcChipID register This read-only register contains the chip identification and hardware version numbers. The firmware must check ...
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Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R R Table 149. Frame Number register (address 0274h) bit description Bit 10.7.4 DcScratch register This 16-bit register can ...
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Table 152. Unlock Device register (address 027Ch) bit allocation Bit 15 14 Reset Bus reset Access W W Bit 7 6 Symbol Reset Bus reset Access W W Table 153. Unlock Device register (address 027Ch) bit description Bit 15 to ...
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Table 156. Test Mode register (address 0284h) bit description Bit Symbol 3 PRBS 2 KSTATE 1 JSTATE 0 SE0_NAK [1] Either FORCEHS or FORCEFS must be set at a time. [2] Of the four bits, PRBS, KSTATE, JSTATE and SE0_NAK, ...
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Power consumption Table 157. Power consumption Number of ports working One port working (high-speed Two ...
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Limiting values Table 158. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V supply voltage CC(5V0) V supply voltage CC(C_IN) I latch-up current lu V electrostatic discharge voltage ...
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Static characteristics Table 160. Static characteristics: digital pins [1] All digital pins , except pins ID, PSW1_N, PSW2_N, PSW3_N and BAT_ON_N. − ° ° +85 C; unless otherwise specified. amb Symbol Parameter V = ...
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Table 162. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3) − 1. 3 CC(I/O) amb Symbol Parameter Output levels for high-speed V high-speed idle level voltage HSOI ...
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Table 165. Static characteristics: V − 1. 3 CC(I/O) amb Symbol Parameter R pull-up resistance on pin V UP(VBUS) R pull-down resistance on pin V DN(VBUS) R idle input resistance on pin ...
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Dynamic characteristics Table 166. Dynamic characteristics: system clock timing − 1. 3 CC(I/O) amb Symbol Parameter Crystal oscillator f clock frequency clk External clock input J external clock jitter δ clock ...
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Table 169. Dynamic characteristics: full-speed source electrical characteristics − 1. 3 CC(I/O) amb Symbol Parameter t differential rise and fall time FRFM matching Z driver output impedance for DRV driver which is ...
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Host timing 15.1.1 PIO timing 15.1.1.1 Register or memory write Fig 19. Register or memory write Table 171. Register or memory write − amb Symbol 1.95 V CC(I/O) t h11 t ...
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Register read Fig 20. Register read Table 172. Register read − amb Symbol 1.95 V CC(I/O) t su12 t su22 t w12 t d12 t d22 ...
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Table 173. Register access − amb Symbol t WHRL t RHRL t RHWL t WHWL [1] For EHCI operational registers, minimum value is 195 ns. 15.1.1.4 Memory read A[17:1] DATA CS_N WR_N RD_N Fig 22. Memory read ...
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Table 174. Memory read − amb Symbol t w13 t su13 t su23 15.1.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity of DREQ is active HIGH 15.1.2.1 Single cycle: ...
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Table 175. DMA read (single cycle) − amb Symbol t a34 t a44 t h14 15.1.2.2 Single cycle: DMA write DREQ DACK WR_N DREQ and DACK are active HIGH. Fig 24. DMA write (single cycle) Table 176. ...
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Multi-cycle: DMA read DREQ and DACK are active HIGH. Fig 25. DMA read (multi-cycle burst) Table 177. DMA read (multi-cycle burst) − amb Symbol 1.95 V CC(I/O) t a16 t a26 ...
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Multi-cycle: DMA write Fig 26. DMA write (multi-cycle burst) Table 178. DMA write (multi-cycle burst) − amb Symbol Parameter 1.95 V CC(I/O) T DMA write cycle time cy17 t data set-up ...
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Peripheral timing 15.2.1 PIO timing 15.2.1.1 PIO register read or write t d68 t d48 CS_N AD[17:1] (read) DATA[31:0] t su18 RD_N t su28 (write) DATA[31:0] WR_N Fig 27. ISP1761 register access timing: separate address and data buses (8051 ...
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Table 179. PIO register read or write − amb Symbol Parameter t CS_N LOW to WR_N LOW delay d68 3.6 V CC(I/O) Reading t RD_N LOW pulse width w18 t address set-up ...
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DMA timing 15.2.2.1 DMA read or write (2) DREQ t su19 (1) DACK t su39 RD_N/WR_N (read) DATA [ (write) DATA [ DREQ is continuously asserted until the last transfer is done or the FIFO ...
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Table 181. DMA read or write − amb Symbol Parameter t DREQ hold time after last strobe on h19 t RD_N/WR_N pulse width w19 t RD_N/WR_N recovery time w29 t read data valid delay after strobe on ...
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Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 DIMENSIONS (mm are the original dimensions) A UNIT A A ...
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TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 0.8 mm ball A1 index area ball A1 ...
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Abbreviations Table 182. Abbreviations Acronym ACK ASIC ATL ATX CS DMA DSC DW EHCI EMI EOP EOS EOT ESD ESR FIFO FS FLS GDMA GPIO GPS HC HNP HS iTD INT ISO ISR ITL LS LSByte MSByte NAK NYET ...
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Table 182. Abbreviations Acronym PIO PLL PMOS POR PORP PTD RAM RISC SE0 SE1 SIE siTD SOF SRAM SRP SS TT UHCI USB 18. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller Interface Specification for Universal ...
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Revision history Table 183. Revision history Revision Release date 9 20100415 Modifications: Globally removed reference to NextPTDPointer. 8 200901130 7 20090812 6 20090121 5 20080313 4 20070305 3 20061127 2 (9397 750 15191) 20051005 1 (9397 750 13258) 20050112 ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 2. Pin description . . . . . . . . . ...
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Table 49. Force Port Enable register (address 0018h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table ...
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Table 103.Address register (address 0200h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Table 104.Mode register (address 020Ch) bit ...
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Table 154.Interrupt Pulse Width register (address 0280h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Table 155.Test Mode register ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 2. Pin configuration (LQFP128); top ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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Device Identification registers 9.5.1.1 Vendor ID register ...
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... Product data sheet Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 09 — 15 April 2010 ISP1761 Hi-Speed USB OTG controller © ST-ERICSSON 2010. All rights reserved. ...