ISP1761BEGE STEricsson, ISP1761BEGE Datasheet - Page 110

• Manufacturer Part Number: ISP1761BEGE
• Manufacturer: STEricsson

Specifications of ISP1761BEGE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 116. Control Function register (address 0228h) bit allocation
[1]
CD00222703
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
10.5.2 Control Function register
R/W
7
0
0
Table 115. Addressing of endpoint buffers
The Control Function register performs the buffer management on endpoints. It consists of
1 byte, and the bit configuration is given in
validate any enabled data endpoint. Before accessing this register, the Endpoint Index
register must first be written to specify the target endpoint.
Table 117. Control Function register (address 0228h) bit description
Buffer name
SETUP
Control OUT
Control IN
Data OUT
Data IN
Bit
7 to 5 -
4
3
reserved
R/W
Symbol
CLBUF
VENDP
6
0
0
[1]
Description
reserved
Clear Buffer: Logic 1 clears the TX or RX buffer of the indexed endpoint. The
RX buffer is automatically cleared once the endpoint is completely read. The TX
buffer is automatically cleared once data is sent over the USB bus. This bit is
set only when it is necessary to forcefully clear the buffer.
Remark: If double buffer is used to clear both the buffers, issue the CLBUF
command two times, that is, set and clear this bit two times. For details on
clearing the buffer, refer to application note ISP1582/83 and ISP1761 clearing
the IN/OUT buffer (AN10045).
Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint for
sending on the next IN token. In general, the endpoint is automatically validated
when its FIFO byte count has reached the endpoint MaxPacketSize. This bit is
set only when it is necessary to validate the endpoint with the FIFO byte count
that is below the Endpoint MaxPacketSize.
R/W
5
0
0
EP0SETUP
1
0
0
0
0
Rev. 09 — 15 April 2010
CLBUF
R/W
4
0
0
VENDP
Table
R/W
3
0
0
ENDPIDX
00h
00h
00h
0Xh
0Xh
116. The register bits can stall, clear or
DSEN
W
2
0
0
Hi-Speed USB OTG controller
STATUS
DIR
0
0
1
0
1
© ST-ERICSSON 2010. All rights reserved.
R/W
1
0
0
ISP1761
STALL
110 of 158
R/W
0
0
0