ISP1761BEGE STEricsson, ISP1761BEGE Datasheet - Page 115

• Manufacturer Part Number: ISP1761BEGE
• Manufacturer: STEricsson

Specifications of ISP1761BEGE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

CD00222703
Product data sheet
10.6 DMA registers
Table 126. Endpoint Type register (address 0208h) bit description
The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the DMA
Command register. The control bits are given in
GDMA read or write (opcode = 00h/01h) for Generic DMA slave mode
The GDMA (slave) can operate in counter mode. RD_N and WR_N are DMA data strobe
signals. These signals are also used as data strobe signals during the PIO access. An
internal multiplex will redirect these signals to the DMA Controller for the DMA transfer or
to registers for the PIO access.
In counter mode, the DIS_XFER_CNT bit in the DcDMAConfiguration register must be set
to logic 0. The DMA Transfer Counter register must be programmed before any DMA
command is issued. The DMA transfer counter is set by writing from the LSByte to the
MSByte (address: 234h to 237h). The DMA transfer count is internally updated only after
the MSByte is written. Once the DMA transfer is started, the transfer counter starts
decrementing and on reaching 0, the DMA_XFER_OK bit is set and an interrupt is
generated by the ISP1761.
The DMA transfer starts once the DMA command is issued. Any of the following three
ways will terminate this DMA transfer:
Bit
15 to 5
4
3
2
1 to 0
•
•
•
Detecting an internal EOT (short packet on an OUT token)
Resetting the DMA
GDMA stop command
Symbol
-
NOEMPKT
ENABLE
DBLBUF
ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type as follows.
Rev. 09 — 15 April 2010
Description
reserved
No Empty Packet: Logic 0 causes the ISP1761 to return a null length
packet for the IN token after the DMA IN transfer is complete. Set to
logic 1 to disable the generation of the null length packet.
Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint.
The memory size is allocated as specified in the Endpoint
MaxPacketSize register. Logic 0 disables the FIFO.
Remark: Stalling a data endpoint will confuse the Data Toggle bit on the
stalled endpoint because the internal logic picks up from where it has
stalled. Therefore, the Data Toggle bit must be reset by disabling and
re-enabling the corresponding endpoint (by setting bit ENABLE to
logic 0, followed by logic 1 in the Endpoint Type register) to reset the
PID.
Double Buffering: Logic 1 enables double buffering for the indexed
endpoint. Logic 0 disables double buffering.
00 — Not used
01 — Isochronous
10 — Bulk
11 — Interrupt
Table
127.
Hi-Speed USB OTG controller
© ST-ERICSSON 2010. All rights reserved.
ISP1761
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