ISP1761BEGE STEricsson, ISP1761BEGE Datasheet - Page 107

• Manufacturer Part Number: ISP1761BEGE
• Manufacturer: STEricsson

Specifications of ISP1761BEGE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

[1]
Table 111. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) bit allocation
CD00222703
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
10.4.5 DcInterruptEnable register
R/W
IEP6TX
7
0
0
R/W
R/W
31
23
0
0
0
0
Table 110. Debug register (address 0212h) bit allocation
This register enables or disables individual interrupt sources. The interrupt for each
endpoint can individually be controlled through the associated IEPnRX or IEPnTX bits,
here n represents the endpoint number. All interrupts can globally be disabled through
bit GLINTENA in the Mode register (see
An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the
USB bus. The interrupt generation depends on Debug mode settings of bit fields
CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0].
All data IN transactions use the Transmit buffers (TX) that are handled by DDBGMODIN
bits. All data OUT transactions go through the Receive buffers (RX) that are handled by
DDBGMODOUT bits. Transactions on control endpoint 0 (IN, OUT and SETUP) are
handled by CDBGMOD bits.
Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up
and high-speed status) can also be individually controlled. A bus reset disables all
enabled interrupts, except bit IEBRST (bus reset) that remains unchanged.
The DcInterruptEnable register consists of 4 bytes. The bit allocation is given in
Bit
15 to 1
0
IEP6RX
R/W
R/W
R/W
6
0
0
30
22
0
0
0
0
Symbol
-
DEBUG
IEP5TX
R/W
R/W
R/W
29
21
5
0
0
0
0
0
0
reserved
Rev. 09 — 15 April 2010
Description
reserved
Always set this bit to logic 0 in both 16-bit and 32-bit accesses.
reserved
IEP5RX
R/W
[1]
R/W
R/W
28
20
4
0
0
0
0
0
0
[1]
Table
IEP4TX
R/W
R/W
R/W
27
19
3
1
1
0
0
0
0
104).
IEP4RX
R/W
R/W
R/W
26
18
2
0
0
0
0
0
0
Hi-Speed USB OTG controller
IEP7TX
IEP3TX
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
25
17
0
0
0
0
1
0
0
ISP1761
IEP7RX
IEP3RX
DEBUG
Table
R/W
R/W
107 of 158
R/W
24
16
0
0
0
0
0
0
0
111.