ISP1761BEGE STEricsson, ISP1761BEGE Datasheet - Page 97

• Manufacturer Part Number: ISP1761BEGE
• Manufacturer: STEricsson

Specifications of ISP1761BEGE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

[1]
Table 98.
CD00222703
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
OTG Timer register (address low word set: 0388h, low word clear: 038Ah; high word set: 038Ch, high
word clear: 038Eh) bit allocation
9.5.4.1 OTG Timer register
B_SESS_
START_
9.5.4 OTG Timer register
R/S/C
R/S/C
R/S/C
R/S/C
END
TMR
31
23
15
7
0
0
0
0
Table 97.
This is a 32-bit register organized as two 16-bit fields. These two fields have separate set
and clear addresses.
Bit
15 to 10
9
8
7
6
5
4
3
2
1
0
BDIS_
ACON
R/S/C
R/S/C
R/S/C
R/S/C
30
22
14
6
0
0
0
0
Symbol
-
OTG_TMR_TIMEOUT
B_SE0_SRP
B_SESS_END
BDIS_ACON
OTG_RESUME
RMT_CONN
ID
DP_SRP
A_B_SESS_VLD
VBUS_VLD
OTG Interrupt Enable Rise register (address set: 0384h, clear: 0386h) bit
description
RESUME
OTG_
R/S/C
R/S/C
R/S/C
R/S/C
29
21
13
5
0
0
0
0
Table 98
Rev. 09 — 15 April 2010
TIMER_INIT_VALUE[23:16]
TIMER_INIT_VALUE[15:8]
CONN
RMT_
R/S/C
R/S/C
R/S/C
R/S/C
shows the bit allocation of the register.
28
20
12
4
0
0
0
0
Description
reserved
IRQ asserted on OTG timer time-out
IRQ asserted when at least 2 ms of SE0 is detected in the
B-idle state
IRQ asserted when V
IRQ asserted on BDIS_ACON condition
IRQ asserted on J-K resume
IRQ asserted on RMT_CONN
IRQ asserted on the ID pin transition from LOW to HIGH
IRQ asserted when DP is asserted during SRP
IRQ asserted on the A-session valid for the A-device or on
the B-session valid for the B-device
IRQ asserted on the rising edge of V
reserved
R/S/C
R/S/C
R/S/C
R/S/C
27
19
11
ID
3
0
0
0
0
[1]
BUS
DP_SRP
R/S/C
R/S/C
R/S/C
R/S/C
is less than 0.8 V
26
18
10
2
0
0
0
0
Hi-Speed USB OTG controller
A_B_SESS
BUS
R/S/C
R/S/C
R/S/C
R/S/C
© ST-ERICSSON 2010. All rights reserved.
_VLD
25
17
1
0
0
0
9
0
ISP1761
VBUS_VLD
R/S/C
R/S/C
R/S/C
R/S/C
97 of 158
24
16
0
0
0
0
8
0