ISP1761BEGE STEricsson, ISP1761BEGE Datasheet - Page 53

• Manufacturer Part Number: ISP1761BEGE
• Manufacturer: STEricsson

Specifications of ISP1761BEGE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 55.
[1]
CD00222703
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Power Down Control register (address 0354h) bit allocation
R/W
R/W
R/W
R/W
31
23
15
0
1
0
7
1
reserved
Table 56.
Bit
31 to 16
15 to 13
12
11
[1]
reserved
[1]
R/W
R/W
R/W
R/W
30
22
14
0
1
0
6
0
Power Down Control register (address 0354h) bit description
[1]
Symbol
CLK_OFF_
COUNTER
[15:0]
-
PORT3_PD Port 3 Pull-Down: Controls port 3 pull-down resistors.
PORT2_PD Port 2 Pull-Down: Controls port 2 pull-down resistors.
BIASEN
R/W
R/W
R/W
R/W
29
21
13
0
1
0
5
1
Rev. 09 — 15 April 2010
Description
Clock Off Counter: Determines the wake-up status duration after any
wake-up event before the ISP1761 goes back into suspend mode.
This time-out is applicable only if, during the given interval, the host
controller is not programmed back to normal functionality.
03E8h — The default value. It determines the default wake-up interval
of 10 ms. A value of zero implies that the host controller never wakes
up on any of the events. This may be useful when using the ISP1761
as a peripheral to save power by permanently programming the host
controller in suspend.
FFFFh — The maximum value. It determines a maximum wake-up
time of 500 ms.
The setting of this register is based on the 100 kHz ± 40 % LazyClock
frequency. It is a multiple of 10 μs period.
Remark: In 16-bit mode, the default value is 17E8h. A write operation
to these bits with any value fixes the clock off counter at 1400h. This
value is equivalent to a fixed wake-up time of 50 ms.
reserved
0 — Port 3 internal pull-down resistors are not connected.
1 — Port 3 internal pull-down resistors are connected.
0 — Port 2 internal pull-down resistors are not connected.
1 — Port 2 internal pull-down resistors are connected.
CLK_OFF_COUNTER[15:8]
CLK_OFF_COUNTER[7:0]
VREG_ON
PORT3_
R/W
R/W
R/W
R/W
PD
28
20
12
0
0
1
4
0
OC3_PWR
PORT2_
R/W
R/W
R/W
R/W
PD
27
19
11
0
1
1
3
0
VBATDET_
OC2_PWR
PWR
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
OC1_PWR
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
25
17
1
0
9
1
1
0
reserved
ISP1761
HC_CLK_
[1]
R/W
R/W
R/W
R/W
EN
53 of 158
24
16
1
0
8
1
0
0