ISP1761BEGE STEricsson, ISP1761BEGE Datasheet - Page 118

• Manufacturer Part Number: ISP1761BEGE
• Manufacturer: STEricsson

Specifications of ISP1761BEGE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 133. DcDMAConfiguration - Device Controller Direct Memory Access Configuration register (address 0238h)
[1]
CD00222703
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
bit allocation
10.6.3 DcDMAConfiguration register
XFER_CNT
R/W
DIS_
R/W
15
0
0
R/W
R/W
7
0
0
15
0
0
7
0
0
Table 132. DMA Transfer Counter register (address 0234h) bit description
This register defines the DMA configuration for GDMA mode. The DcDMAConfiguration
register consists of 2 bytes. The bit allocation is given in
Table 134. DcDMAConfiguration - Device Controller Direct Memory Access Configuration
Bit
31 to 24
23 to 16
15 to 8
7 to 0
Bit
15 to 8
7
6 to 4
R/W
R/W
14
0
0
R/W
R/W
6
0
0
14
0
0
6
0
0
Symbol
-
DIS_XFER_CNT
-
register (address 0238h) bit description
Symbol
DMACR4, DMACR[31:24]
DMACR3, DMACR[23:16]
DMACR2, DMACR[15:8]
DMACR1, DMACR[7:0]
reserved
R/W
R/W
13
0
0
5
0
0
R/W
R/W
13
0
0
5
0
0
Rev. 09 — 15 April 2010
[1]
Description
reserved
Disable Transfer Counter: Write logic 0 to perform DMA operation.
Logic 1 disables the DMA transfer counter (see
reserved
DMACR2 = DMACR[15:8]
DMACR1 = DMACR[7:0]
R/W
R/W
12
R/W
R/W
0
0
4
0
0
12
0
0
4
0
0
reserved
Description
DMA Counter 4: DMA transfer counter byte 4
DMA Counter 3: DMA transfer counter byte 3
DMA Counter 2: DMA transfer counter byte 2
DMA Counter 1: DMA transfer counter byte 1
[1]
R/W
R/W
11
R/W
R/W
0
0
3
0
0
11
0
0
3
0
0
MODE[1:0]
R/W
R/W
Table
R/W
R/W
10
0
0
2
0
0
Hi-Speed USB OTG controller
10
0
0
2
0
0
133.
reserved
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
9
0
0
1
0
0
9
0
0
1
0
0
Table
ISP1761
131).
WIDTH
118 of 158
R/W
R/W
R/W
R/W
8
0
0
0
1
1
8
0
0
0
0
0