XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 130

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Block RAM
130
Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B])
Optional Output Register On/Off Switch - DO[A|B]_REG
Extended Mode Address Determinant - RAM_EXTENSION_[A|B]
Read Width - READ_WIDTH_[A|B]
Write Width - WRITE_WIDTH_[A|B]
Write Mode - WRITE_MODE_[A|B]
The SRVAL (single-port) or SRVAL_A and SRVAL_B (dual-port) attributes define output
latch values when the SSR input is asserted. The width of the SRVAL (SRVAL_A and
SRVAL_B) attribute is the port width, as shown in
encoded bit vectors and the default value is 0. This attribute sets the value of the output
register when the optional output register attribute is set. When the register is not used, the
latch gets set to the SRVAL instead. In the 36-bit mode, SRVAL[35:32] corresponds to
DP[3:0].
Table 4-10: Port Width Values
This attribute sets the number of pipeline register at A/B output of the block RAM. The
valid values are 0 (default) or 1.
This attribute determines whether the block RAM of interest has its A/B port as
UPPER/LOWER address when using the cascade mode. Refer to the
RAM
NONE.
This attribute determines the A/B read port width of the block RAM. The valid values are:
0 (default), 1, 2, 4, 9, 18, and 36.
This attribute determines the A/B write port width of the block RAM. The valid values are:
0 (default), 1, 2, 4, 9, 18, and 36.
This attribute determines the write mode of the A/B input ports. The possible values are
WRITE_FIRST (default), READ_FIRST, and NO_CHANGE. Additional information on the
write modes is in the
Port Data Width
section. When the block RAM is not used in cascade mode, the default value is
18
36
1
2
4
9
Write Modes
www.xilinx.com
DOP Bus
<1:0>
<3:0>
<0>
NA
NA
NA
section.
Table
DO Bus
<15:0>
<31:0>
<1:0>
<3:0>
<7:0>
<0>
4-10. These attributes are hex-
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Cascadable Block
INIT / SRVAL
(4 + 32) = 36
(2 + 16) = 18
(1 + 8) = 9
1
2
4